Codegen: LICM Remove check for exactly 1 register def.

[iteratee]

Summary

When considering whether to split an instruction with a memory operand
into an explicit load and a register-based instruction, we currently
check that the resulting instruction has exactly 1 def. This prevents 2
important LICM optimizations: compares with memory operands, and double
inderect calls. All the tests and the test-suite pass without the check.
My guess as to original intent is to limit the additional register pressure
created by the new instruction, but given that we only split out a single
register, it is already limited.

The licm-dominance test now checks actual memory loads for hoisting instead of
undef, and it tests compares.
hoist-invariant-load.ll now checks for 2 hoists, the intended hoist, and a bonus
from calling a got-relative function in a loop.

[iteratee]

Corrected the output of the non-hoisted loads.

[iteratee]

Quentin, Andrew,

Functionally this is a one-line change. When splitting an instruction from a memory op to an explicit load and a register op, we were checking the number of register defs in the resulting register op, and bailing if it wasn't exactly one. I've thought carefully about it, and the check doesn't seem to be necessary, and the tests all pass, but I'd like someone more familiar with that code to look over it.

Thanks,
Kyle.

[atrick]

Frankly I don't understand what MID.getNumDefs() has to do with anything here. So your change looks ok to me. But I'm not clear on how the register form of the instruction ends up with multiple defs--I guess it already had multiple defs. Can you show an example of that in the form of machine instrs?

[iteratee]

Sure. I should be able to find an example with multiple defs.

[iteratee]

Andrew, there's a test with a multiple register-def instruction in D21627.
The existing tests now cover 0-def instructions, as the double-indirection for the call gets hoisted to a single indirection.

I couldn't put the test in this revision, because memory-refs were not being propagated for the folded load in the instruction in question.

[atrick]

LGTM

lib/CodeGen/MachineLICM.cpp

MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
   unsigned LoadRegIndex;
   unsigned NewOpc =
     TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
                                     /*UnfoldLoad=*/true,
                                     /*UnfoldStore=*/false,
                                     &LoadRegIndex);
   if (NewOpc == 0) return nullptr;
   const MCInstrDesc &MID = TII->get(NewOpc);
-  if (MID.getNumDefs() != 1) return nullptr;
   MachineFunction &MF = *MI->getParent()->getParent();
   const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
   // Ok, we're unfolding. Create a temporary register and do the unfold.
   unsigned Reg = MRI->createVirtualRegister(RC);
 
   SmallVector<MachineInstr *, 2> NewMIs;
   bool Success =
     TII->unfoldMemoryOperand(MF, MI, Reg,

test/CodeGen/X86/hoist-invariant-load.ll

 ; REQUIRES: asserts
-; RUN: llc < %s -stats -O2 2>&1 | grep "1 machine-licm"
+; RUN: llc < %s -stats -O2 2>&1 | grep "2 machine-licm"
+; 2 invariant loads, 1 for OBJC_SELECTOR_REFERENCES_
+; and 1 for objc_msgSend from the GOT
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.7.2"
 
 @"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__objc_methname,cstring_literals", align 1
 @"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i64 0, i64 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 @"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__DATA, __objc_imageinfo, regular, no_dead_strip"
 @llvm.used = appending global [3 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*)], section "llvm.metadata"

test/CodeGen/X86/licm-dominance.ll

 ; RUN: llc -asm-verbose=true < %s | FileCheck %s
 
 ; MachineLICM should check dominance before hoisting instructions.
+; only the load of a0 is guaranteed to execute, so only it can be hoisted.
+; CHECK: movb (%rdi), [[a0reg:%[a-z0-9]+]]
+; CHECK: ## %for.body.i
+; CHECK: testb [[a0reg]], [[a0reg]]
 ; CHECK: ## in Loop:
-; CHECK-NEXT: xorl  %eax, %eax
-; CHECK-NEXT: testb %al, %al
+; CHECK: cmpb $1
+; CHECK: cmpb $2
+; CHECK: cmpb $3
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-macosx10.7.2"
 
-define void @CMSColorWorldCreateParametricData() nounwind uwtable optsize ssp {
+define void @CMSColorWorldCreateParametricData(
+    i8* dereferenceable(1) %a0,
+    i8* dereferenceable(1) %a1,
+    i8* dereferenceable(1) %a2,
+    i8* dereferenceable(1) %a3,
+    i64 %count) nounwind uwtable optsize ssp readonly {
 entry:
   br label %for.body.i
 
-for.body.i:                                       
-  br i1 undef, label %for.inc.i, label %if.then26.i
+for.body.i:
+  %i = phi i64 [0, %entry], [%i.inc, %for.inc.i]
+  %0 = load i8, i8* %a0, !invariant.load !0
+  %cond0 = icmp eq i8 %0, 0
+  br i1 %cond0, label %for.inc.i, label %if.then26.i
 
-if.then26.i:                                      
-  br i1 undef, label %if.else.i.i, label %lor.lhs.false.i.i
+if.then26.i:
+  %1 = load i8, i8* %a1, !invariant.load !0
+  %cond1 = icmp eq i8 %1, 1
+  br i1 %cond1, label %if.else.i.i, label %lor.lhs.false.i.i
 
-if.else.i.i:                                      
-  br i1 undef, label %lor.lhs.false.i.i, label %if.then116.i.i
+if.else.i.i:
+  %2 = load i8, i8* %a2, !invariant.load !0
+  %cond2 = icmp eq i8 %2, 2
+  br i1 %cond2, label %lor.lhs.false.i.i, label %for.inc.i
 
-lor.lhs.false.i.i:                                
-  br i1 undef, label %for.inc.i, label %if.then116.i.i
-
-if.then116.i.i:                                   
-  unreachable
+lor.lhs.false.i.i:
+  %3 = load i8, i8* %a3, !invariant.load !0
+  %cond3 = icmp eq i8 %3, 3
+  br i1 %cond3, label %for.inc.i, label %if.end28.i
 
-for.inc.i:                                        
-  %cmp17.i = icmp ult i64 undef, undef
+for.inc.i:
+  %i.inc = add nsw i64 %i, 1
+  %cmp17.i = icmp ult i64 %i.inc, %count
   br i1 %cmp17.i, label %for.body.i, label %if.end28.i
 
-if.end28.i:                                       
+if.end28.i:
   ret void
 }
+
+!0 = !{}