Legalize FMINNAN and FMAXNAN during float16 promotion

[pirama]

Summary

Folding of setcc + select to fminnan or fmaxnan can happen for float16
since this folding is conditioned on the eventual legalized type (float,
in this case). Promote result of FMINNAN and FMAXNAN nodes just like
other binary nodes.

[ab]

Is this r271317?

Feel free to add the tests though (nm in particular).

[pirama]

In D21009#449432, @ab wrote:

Is this r271317?

Yes, you are correct :) My tree was slightly older than this revision and hence I missed it. I'll upload a patch tomorrow with just the nm test.

lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

switch (N->getOpcode()) {
     case ISD::FSIN:
     case ISD::FSQRT:
     case ISD::FTRUNC:     R = PromoteFloatRes_UnaryOp(N); break;
 
     // Binary FP Operations
     case ISD::FADD:
     case ISD::FDIV:
     case ISD::FMAXNUM:
+    case ISD::FMAXNAN:
     case ISD::FMINNUM:
+    case ISD::FMINNAN:
     case ISD::FMUL:
     case ISD::FPOW:
     case ISD::FREM:
     case ISD::FSUB:       R = PromoteFloatRes_BinOp(N); break;
 
     case ISD::FMA:        // FMA is same as FMAD
     case ISD::FMAD:       R = PromoteFloatRes_FMAD(N); break;
 

test/CodeGen/ARM/fp16-promote.ll

 ; CHECK-FP16-DAG: vcvtb.f16.f32
 ; CHECK-LIBCALL-DAG: bl __aeabi_f2h
 define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 {
   %c = sitofp i32 %a to half
   %r = fadd half %b, %c
   ret half %r
 }
 
+; CHECK-LABEL: test_f16_fminmaxnan:
+; CHECK: vmin.f32
+; CHECK: vmax.f32
+define half @test_f16_fminmaxnan(half %p) #0 {
+  %cmp1 = fcmp ugt half 0xHBC00, %p
+  %cond1 = select i1 %cmp1, half %p, half 0xHBC00
+  %cmp2 = fcmp ult half 0xHBC99, %cond1
+  %cond2 = select i1 %cmp2, half %cond1, half 0xHBC99
+  ret half %cond2
+}
+
 attributes #0 = { nounwind }

test/CodeGen/ARM/vminmaxnm.ll

 ; CHECK: vmaxnm.f32
   %cmp1 = fcmp fast ule float -0., %a
   %cond1 = select i1 %cmp1, float -0., float %a
   %cmp2 = fcmp fast oge float -0., %cond1
   %cond2 = select i1 %cmp2, float -0., float %cond1
   ret float %cond2
 }
 
+define half @fp-armv8_vminmaxnm_f16_promote(half %p) #0 {
+; CHECK-LABEL: "fp-armv8_vminmaxnm_f16_promote":
+; CHECK-NOT: vcmp
+; CHECK: vminnm.f32
+; CHECK: vmaxnm.f32
+  %cmp1 = fcmp fast ugt half 0xHBC00, %p
+  %cond1 = select i1 %cmp1, half %p, half 0xHBC00
+  %cmp2 = fcmp fast ult half 0xHBC99, %cond1
+  %cond2 = select i1 %cmp2, half %cond1, half 0xHBC99
+  ret half %cond2
+}
+
+
 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
 declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
 declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone