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Differential D19915

Adding back-end support to two bit scanning intrinsics
ClosedPublic

Authored by opaparo on May 4 2016, 5:54 AM.

Details

Reviewers
RKSimon
AsafBadouh
igorb
m_zuckerman
Commits
rG6a894956fccd: Adding back-end support to two bit scanning intrinsics
rL271386: Adding back-end support to two bit scanning intrinsics
Summary

Adding LLVM back-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
Their functionality is as described in Intel intrinsics guide:
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

Diff Detail

Repository
rL LLVM

Event Timeline

opaparo updated this revision to Diff 56132.May 4 2016, 5:54 AM
opaparo retitled this revision from to Adding back-end support to two bit scanning intrinsics.
opaparo updated this object.
opaparo added reviewers: m_zuckerman, AsafBadouh, igorb.May 4 2016, 6:23 AM
AsafBadouh added inline comments.May 4 2016, 6:43 AM
test/CodeGen/X86/bitscan.ll
1 ↗(On Diff #56132)

please change "-mcpu=core-avx-i -mattr=+rdrnd " to "-mcpu=corei7"

6 ↗(On Diff #56132)

add CHECK-LABE

11 ↗(On Diff #56132)

same

m_zuckerman edited edge metadata.EditedMay 4 2016, 6:47 AM
This comment has been deleted.
include/llvm/IR/IntrinsicsX86.td
8722 ↗(On Diff #56132)

Add more one line

test/CodeGen/X86/bitscan.ll
1 ↗(On Diff #56132)

Why you need -mcpu=core-avx-i?

16 ↗(On Diff #56132)

Add more one line

m_zuckerman added inline comments.May 4 2016, 6:49 AM
include/llvm/IR/IntrinsicsX86.td
8716 ↗(On Diff #56132)

convention: add _ia32

8719 ↗(On Diff #56132)

convention: add _ia32

opaparo updated this revision to Diff 56532.May 9 2016, 12:41 AM
opaparo edited edge metadata.
RKSimon added a reviewer: RKSimon.May 9 2016, 5:38 AM
RKSimon added a subscriber: RKSimon.
RKSimon added inline comments.
include/llvm/IR/IntrinsicsX86.td
8719 ↗(On Diff #56532)

Why doesn't the patch include support for the 16 and 64 bit BSR/BSF instructions as well?

As Michael said, even if the 16 and 64 bit versions aren't included in this patch the intrinsic naming convention should include the type size for consistency if/when they are added added in the future.

opaparo updated this revision to Diff 56711.May 10 2016, 7:00 AM
opaparo added inline comments.May 10 2016, 7:32 AM
include/llvm/IR/IntrinsicsX86.td
8719 ↗(On Diff #56532)

As my implementation follows Intel's Intrinsics guide, the only version of this form of BSR/BSF intrinsics, as specified in the guide, is the 32-bit version. There is another form of the BSR/BSF intrinsics, which has a 32-bit version as well as a 64-bit version, but this form is fully implemented as part of the front-end and has no back-end part.
As for the naming convention - the appropriate change was made.

RKSimon edited edge metadata.May 13 2016, 5:48 AM

Couple of minors

test/CodeGen/X86/bitscan.ll
1 ↗(On Diff #56711)

Please can you test with a 32-bit triple as well?

11 ↗(On Diff #56711)

Please run the file through the utils\update_llc_test_checks.py script to test the codegen more thoroughly.

opaparo updated this revision to Diff 57466.May 17 2016, 5:19 AM
opaparo edited edge metadata.

Added 32-bit test for the intrinsics

RKSimon accepted this revision.May 23 2016, 7:31 AM
RKSimon edited edge metadata.

LGTM

This revision is now accepted and ready to land.May 23 2016, 7:31 AM
opaparo added a child revision: D19914: Adding front-end support to several intrinsics (bit scanning, conversion and state reading intrinsics).May 24 2016, 12:34 AM
AsafBadouh accepted this revision.May 25 2016, 12:36 AM
AsafBadouh edited edge metadata.

LGTM

Closed by commit rL271386: Adding back-end support to two bit scanning intrinsics (authored by mzuckerm). · Explain WhyJun 1 2016, 5:09 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
IR/
10 lines
lib/
Target/
X86/
2 lines
test/
CodeGen/
X86/
23 lines

Diff 59203

llvm/trunk/include/llvm/IR/IntrinsicsX86.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,436 Lines • ▼ Show 20 Lines
let TargetPrefix = "x86" in { let TargetPrefix = "x86" in {
def int_x86_monitorx def int_x86_monitorx
: GCCBuiltin<"__builtin_ia32_monitorx">, : GCCBuiltin<"__builtin_ia32_monitorx">,
Intrinsic<[], [ llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty ], []>; Intrinsic<[], [ llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty ], []>;
def int_x86_mwaitx def int_x86_mwaitx
: GCCBuiltin<"__builtin_ia32_mwaitx">, : GCCBuiltin<"__builtin_ia32_mwaitx">,
Intrinsic<[], [ llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ], []>; Intrinsic<[], [ llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ], []>;
} }
//===----------------------------------------------------------------------===//
// Bit Scan intrinsics
let TargetPrefix = "x86" in {
def int_x86_bit_scan_forward_32 : GCCBuiltin<"__builtin_ia32_bit_scan_forward">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_x86_bit_scan_reverse_32 : GCCBuiltin<"__builtin_ia32_bit_scan_reverse">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
}

llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h

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X86_INTRINSIC_DATA(avx512_vcvtss2si32, INTR_TYPE_2OP, X86_INTRINSIC_DATA(avx512_vcvtss2si32, INTR_TYPE_2OP,
X86ISD::SCALAR_FP_TO_SINT_RND, 0), X86ISD::SCALAR_FP_TO_SINT_RND, 0),
X86_INTRINSIC_DATA(avx512_vcvtss2si64, INTR_TYPE_2OP, X86_INTRINSIC_DATA(avx512_vcvtss2si64, INTR_TYPE_2OP,
X86ISD::SCALAR_FP_TO_SINT_RND, 0), X86ISD::SCALAR_FP_TO_SINT_RND, 0),
X86_INTRINSIC_DATA(avx512_vcvtss2usi32, INTR_TYPE_2OP, X86_INTRINSIC_DATA(avx512_vcvtss2usi32, INTR_TYPE_2OP,
X86ISD::SCALAR_FP_TO_UINT_RND, 0), X86ISD::SCALAR_FP_TO_UINT_RND, 0),
X86_INTRINSIC_DATA(avx512_vcvtss2usi64, INTR_TYPE_2OP, X86_INTRINSIC_DATA(avx512_vcvtss2usi64, INTR_TYPE_2OP,
X86ISD::SCALAR_FP_TO_UINT_RND, 0), X86ISD::SCALAR_FP_TO_UINT_RND, 0),
X86_INTRINSIC_DATA(bit_scan_forward_32, INTR_TYPE_1OP, X86ISD::BSF, 0),
X86_INTRINSIC_DATA(bit_scan_reverse_32, INTR_TYPE_1OP, X86ISD::BSR, 0),
X86_INTRINSIC_DATA(fma_vfmadd_pd, INTR_TYPE_3OP, X86ISD::FMADD, 0), X86_INTRINSIC_DATA(fma_vfmadd_pd, INTR_TYPE_3OP, X86ISD::FMADD, 0),
X86_INTRINSIC_DATA(fma_vfmadd_pd_256, INTR_TYPE_3OP, X86ISD::FMADD, 0), X86_INTRINSIC_DATA(fma_vfmadd_pd_256, INTR_TYPE_3OP, X86ISD::FMADD, 0),
X86_INTRINSIC_DATA(fma_vfmadd_ps, INTR_TYPE_3OP, X86ISD::FMADD, 0), X86_INTRINSIC_DATA(fma_vfmadd_ps, INTR_TYPE_3OP, X86ISD::FMADD, 0),
X86_INTRINSIC_DATA(fma_vfmadd_ps_256, INTR_TYPE_3OP, X86ISD::FMADD, 0), X86_INTRINSIC_DATA(fma_vfmadd_ps_256, INTR_TYPE_3OP, X86ISD::FMADD, 0),
X86_INTRINSIC_DATA(fma_vfmaddsub_pd, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0), X86_INTRINSIC_DATA(fma_vfmaddsub_pd, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0),
X86_INTRINSIC_DATA(fma_vfmaddsub_pd_256, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0), X86_INTRINSIC_DATA(fma_vfmaddsub_pd_256, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0),
X86_INTRINSIC_DATA(fma_vfmaddsub_ps, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0), X86_INTRINSIC_DATA(fma_vfmaddsub_ps, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0),
X86_INTRINSIC_DATA(fma_vfmaddsub_ps_256, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0), X86_INTRINSIC_DATA(fma_vfmaddsub_ps_256, INTR_TYPE_3OP, X86ISD::FMADDSUB, 0),
▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/bitscan.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=64-BIT
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=32-BIT
declare i32 @llvm.x86.bit.scan.forward.32(i32 %val)
declare i32 @llvm.x86.bit.scan.reverse.32(i32 %val)
define i32 @test_bsf(i32 %val) {
%call = call i32 @llvm.x86.bit.scan.forward.32(i32 %val)
ret i32 %call
; ALL-LABEL: test_bsf:
; 64-BIT: bsfl %edi, %eax
; 32-BIT: bsfl 4(%esp), %eax
}
define i32 @test_bsr(i32 %val) {
%call = call i32 @llvm.x86.bit.scan.reverse.32(i32 %val)
ret i32 %call
; ALL-LABEL: test_bsr:
; 64-BIT: bsrl %edi, %eax
; 32-BIT: bsrl 4(%esp), %eax
}