[SPARC] [SSP] Add support for LOAD_STACK_GUARD.

[• koriakin]

Summary

This fixes PR22248 on sparc.

[jyknight]

Looks reasonable. OK, with requested comment addition.

(BTW: the current interface in llvm for overriding the behavior of SSP seems unnecessarily confusing, I hope that gets cleaned up at some point.)

lib/Target/Sparc/SparcInstrInfo.cpp

500 ↗

(On Diff #54568)

Is there some ABI documentation that mentions these offsets? Or is this simply offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc?

Can you add a comment here, whatever the source?

[• koriakin]

In D19386#411664, @jyknight wrote:

Looks reasonable. OK, with requested comment addition.

(BTW: the current interface in llvm for overriding the behavior of SSP seems unnecessarily confusing, I hope that gets cleaned up at some point.)

Yeah, there are several, and it's a mess. The LOAD_STACK_GUARD is the most confusing so far, with the justification that it avoids spilling the correct guard onto the stack, thus nullifying the protection...

lib/Target/Sparc/SparcInstrInfo.cpp

500 ↗

(On Diff #54568)

I'm afraid not, it's just offsetof in tcbhead_t. I copied these from gcc. I'll add a comment.

llvm/trunk/lib/Target/Sparc/SparcISelLowering.h

public:
 
     /// If a physical register, this returns the register that receives the
     /// exception typeid on entry to a landing pad.
     unsigned
     getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
       return SP::I1;
     }
 
+    /// Override to support customized stack guard loading.
+    bool useLoadStackGuardNode() const override;
+    void insertSSPDeclarations(Module &M) const override;
+
     /// getSetCCResultType - Return the ISD::SETCC ValueType
     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                            EVT VT) const override;
 
     SDValue
       LowerFormalArguments(SDValue Chain,
                            CallingConv::ID CallConv,
                            bool isVarArg,

llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

case ISD::LOAD: {
 
     SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
     Results.push_back(Res);
     Results.push_back(LoadRes.getValue(1));
     return;
   }
   }
 }
+
+// Override to enable LOAD_STACK_GUARD lowering on Linux.
+bool SparcTargetLowering::useLoadStackGuardNode() const {
+  if (!Subtarget->isTargetLinux())
+    return TargetLowering::useLoadStackGuardNode();
+  return true;
+}
+
+// Override to disable global variable loading on Linux.
+void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
+  if (!Subtarget->isTargetLinux())
+    return TargetLowering::insertSSPDeclarations(M);
+}

llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h

public:
 
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIndex,
                             const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
 
   unsigned getGlobalBaseReg(MachineFunction *MF) const;
+
+  // Lower pseudo instructions after register allocation.
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 };
 
 }
 
 #endif

llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp

unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
   GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
 
   DebugLoc dl;
 
   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
   SparcFI->setGlobalBaseReg(GlobalBaseReg);
   return GlobalBaseReg;
 }
+
+bool SparcInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
+  switch (MI->getOpcode()) {
+  case TargetOpcode::LOAD_STACK_GUARD: {
+    assert(Subtarget->isTargetLinux() &&
+           "Only Linux target is expected to contain LOAD_STACK_GUARD");
+    // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
+    const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
+    MI->setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
+    MachineInstrBuilder(*MI->getParent()->getParent(), MI)
+        .addReg(SP::G7).addImm(Offset);
+    return true;
+  }
+  }
+  return false;
+}

llvm/trunk/lib/Target/Sparc/SparcSubtarget.h

 
 #define GET_SUBTARGETINFO_HEADER
 #include "SparcGenSubtargetInfo.inc"
 
 namespace llvm {
 class StringRef;
 
 class SparcSubtarget : public SparcGenSubtargetInfo {
+  Triple TargetTriple;
   virtual void anchor();
   bool IsV9;
   bool IsLeon;
   bool V8DeprecatedInsts;
   bool IsVIS, IsVIS2, IsVIS3;
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
public:
   int64_t getStackPointerBias() const {
     return is64Bit() ? 2047 : 0;
   }
 
   /// Given a actual stack size as determined by FrameInfo, this function
   /// returns adjusted framesize which includes space for register window
   /// spills and arguments.
   int getAdjustedFrameSize(int stackSize) const;
+
+  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 };
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp

if (!IsV9)
     UsePopc = false;
 
   return *this;
 }
 
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, TargetMachine &TM,
                                bool is64Bit)
-    : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
+    : SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
 
 int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
 
   if (is64Bit()) {
     // All 64-bit stack frames must be 16-byte aligned, and must reserve space
     // for spilling the 16 window registers at %sp+BIAS..%sp+BIAS+128.

llvm/trunk/test/CodeGen/SPARC/stack-protector.ll

+; RUN: llc -mtriple=sparc-unknown-linux < %s | FileCheck %s --check-prefix=LINUX-32
+; RUN: llc -mtriple=sparc64-unknown-linux < %s | FileCheck %s --check-prefix=LINUX-64
+; RUN: llc -mtriple=sparc-unknown-solaris < %s | FileCheck %s --check-prefix=GENERIC
+; RUN: llc -mtriple=sparc64-unknown-solaris < %s | FileCheck %s --check-prefix=GENERIC
+
+; LINUX-32: ld [%g7+20], [[REG1:%[ilo][0-9]*]]
+; LINUX-64: ldx [%g7+40], [[REG1:%[ilo][0-9]*]]
+; LINUX-32-NOT: __stack_chk_guard
+; LINUX-64-NOT: __stack_chk_guard
+; GENERIC: __stack_chk_guard
+
+@"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00"    ; <[11 x i8]*> [#uses=1]
+
+define void @test(i8* %a) nounwind ssp {
+entry:
+  %a_addr = alloca i8*    ; <i8**> [#uses=2]
+  %buf = alloca [8 x i8]    ; <[8 x i8]*> [#uses=2]
+  %"alloca point" = bitcast i32 0 to i32    ; <i32> [#uses=0]
+  store i8* %a, i8** %a_addr
+  %buf1 = bitcast [8 x i8]* %buf to i8*    ; <i8*> [#uses=1]
+  %0 = load i8*, i8** %a_addr, align 4    ; <i8*> [#uses=1]
+  %1 = call i8* @strcpy(i8* %buf1, i8* %0) nounwind    ; <i8*> [#uses=0]
+  %buf2 = bitcast [8 x i8]* %buf to i8*    ; <i8*> [#uses=1]
+  %2 = call i32 (i8*, ...) @printf(i8* getelementptr ([11 x i8], [11 x i8]* @"\01LC", i32 0, i32 0), i8* %buf2) nounwind    ; <i32> [#uses=0]
+  br label %return
+
+return:   ; preds = %entry
+  ret void
+}
+
+declare i8* @strcpy(i8*, i8*) nounwind
+
+declare i32 @printf(i8*, ...) nounwind