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Differential D19318

[InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 2)
ClosedPublic

Authored by RKSimon on Apr 20 2016, 5:10 AM.

Details

Reviewers
spatel
ab
majnemer
mkuper
Commits
rG83020942d32f: [InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 2 of 2)
rL267357: [InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 2 of 2)
Summary

Split from D17490. This patch improves support for determining the demanded vector elements through SSE scalar intrinsics:

1 - demanded vector element support for unary and some extra binary scalar intrinsics (RCP/RSQRT/SQRT/FRCZ and ADD/CMP/DIV/ROUND).
2 - addss/addsd get simplified to a fadd call if we aren't interested in the pass through elements
3 - if we don't need the lowest element of a scalar operation then just use the first argument (the pass through elements) directly

We can add support for propagating demanded elements through any equivalent packed SSE intrinsics in a future patch (these wouldn't use the pass through patterns).

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 54346.Apr 20 2016, 5:10 AM
RKSimon retitled this revision from to [InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 2).
RKSimon updated this object.
RKSimon added reviewers: majnemer, mkuper, ab, spatel.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
RKSimon mentioned this in D17490: [InstCombine][SSE] Demanded vector elements for scalar intrinsics.Apr 20 2016, 5:21 AM
RKSimon added inline comments.Apr 20 2016, 5:23 AM
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
1236 ↗(On Diff #54346)

I'm trying to work out if we need to be worried about rounding/exceptions checks for DIVSS/DIVSD - we have no equivalent packed intrinsics they always use FDIV.

spatel added inline comments.Apr 20 2016, 6:04 PM
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
1236 ↗(On Diff #54346)

How is div different than the other math ops?

RKSimon added inline comments.Apr 21 2016, 5:22 AM
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
1236 ↗(On Diff #54346)

Turns out it isn't - we can safely add the DIVSS/DIVSD -> FDIV conversion

spatel accepted this revision.Apr 21 2016, 7:32 AM
spatel edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 21 2016, 7:32 AM
Closed by commit rL267357: [InstCombine][SSE] Demanded vector elements for scalar intrinsics (Part 2 of 2) (authored by RKSimon). · Explain WhyApr 24 2016, 11:28 AM
This revision was automatically updated to reflect the committed changes.
RKSimon mentioned this in rL267359: [InstCombine][SSE] Reduce DIVSS/DIVSD to FDIV if only first element is required.Apr 24 2016, 11:41 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Transforms/
InstCombine/
39 lines
test/
Transforms/
InstCombine/
122 lines
76 lines
14 lines
30 lines

Diff 54806

llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Show First 20 Lines • Show All 1,173 Lines • ▼ Show 20 Lines case Instruction::FPExt:
break; break;
case Instruction::Call: { case Instruction::Call: {
IntrinsicInst *II = dyn_cast<IntrinsicInst>(I); IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
if (!II) break; if (!II) break;
switch (II->getIntrinsicID()) { switch (II->getIntrinsicID()) {
default: break; default: break;
// Unary vector operations that work column-wise.
case Intrinsic::x86_sse_rcp_ss:
case Intrinsic::x86_sse_rsqrt_ss:
case Intrinsic::x86_sse_sqrt_ss:
case Intrinsic::x86_sse2_sqrt_sd:
case Intrinsic::x86_xop_vfrcz_ss:
case Intrinsic::x86_xop_vfrcz_sd:
TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
UndefElts, Depth + 1);
if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
// If lowest element of a scalar op isn't used then use Arg0.
if (DemandedElts.getLoBits(1) != 1)
return II->getArgOperand(0);
// TODO: If only low elt lower SQRT to FSQRT (with rounding/exceptions checks).
break;
// Binary vector operations that work column-wise. A dest element is a // Binary vector operations that work column-wise. A dest element is a
// function of the corresponding input elements from the two inputs. // function of the corresponding input elements from the two inputs.
case Intrinsic::x86_sse_add_ss:
case Intrinsic::x86_sse_sub_ss: case Intrinsic::x86_sse_sub_ss:
case Intrinsic::x86_sse_mul_ss: case Intrinsic::x86_sse_mul_ss:
case Intrinsic::x86_sse_div_ss:
case Intrinsic::x86_sse_min_ss: case Intrinsic::x86_sse_min_ss:
case Intrinsic::x86_sse_max_ss: case Intrinsic::x86_sse_max_ss:
case Intrinsic::x86_sse_cmp_ss:
case Intrinsic::x86_sse2_add_sd:
case Intrinsic::x86_sse2_sub_sd: case Intrinsic::x86_sse2_sub_sd:
case Intrinsic::x86_sse2_mul_sd: case Intrinsic::x86_sse2_mul_sd:
case Intrinsic::x86_sse2_div_sd:
case Intrinsic::x86_sse2_min_sd: case Intrinsic::x86_sse2_min_sd:
case Intrinsic::x86_sse2_max_sd: case Intrinsic::x86_sse2_max_sd:
case Intrinsic::x86_sse2_cmp_sd:
case Intrinsic::x86_sse41_round_ss:
case Intrinsic::x86_sse41_round_sd:
TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts, TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
UndefElts, Depth + 1); UndefElts, Depth + 1);
if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; } if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts, TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
UndefElts2, Depth + 1); UndefElts2, Depth + 1);
if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; } if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
// If only the low elt is demanded and this is a scalarizable intrinsic, // If only the low elt is demanded and this is a scalarizable intrinsic,
// scalarize it now. // scalarize it now.
if (DemandedElts == 1) { if (DemandedElts == 1) {
switch (II->getIntrinsicID()) { switch (II->getIntrinsicID()) {
default: break; default: break;
case Intrinsic::x86_sse_add_ss:
case Intrinsic::x86_sse_sub_ss: case Intrinsic::x86_sse_sub_ss:
case Intrinsic::x86_sse_mul_ss: case Intrinsic::x86_sse_mul_ss:
case Intrinsic::x86_sse2_add_sd:
case Intrinsic::x86_sse2_sub_sd: case Intrinsic::x86_sse2_sub_sd:
case Intrinsic::x86_sse2_mul_sd: case Intrinsic::x86_sse2_mul_sd:
// TODO: Lower MIN/MAX/ABS/etc // TODO: Lower MIN/MAX/etc.
// TODO: Lower DIV (with rounding/exceptions checks).
Value *LHS = II->getArgOperand(0); Value *LHS = II->getArgOperand(0);
Value *RHS = II->getArgOperand(1); Value *RHS = II->getArgOperand(1);
// Extract the element as scalars. // Extract the element as scalars.
LHS = InsertNewInstWith(ExtractElementInst::Create(LHS, LHS = InsertNewInstWith(ExtractElementInst::Create(LHS,
ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II);
RHS = InsertNewInstWith(ExtractElementInst::Create(RHS, RHS = InsertNewInstWith(ExtractElementInst::Create(RHS,
ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II);
switch (II->getIntrinsicID()) { switch (II->getIntrinsicID()) {
default: llvm_unreachable("Case stmts out of sync!"); default: llvm_unreachable("Case stmts out of sync!");
case Intrinsic::x86_sse_add_ss:
case Intrinsic::x86_sse2_add_sd:
TmpV = InsertNewInstWith(BinaryOperator::CreateFAdd(LHS, RHS,
II->getName()), *II);
break;
case Intrinsic::x86_sse_sub_ss: case Intrinsic::x86_sse_sub_ss:
case Intrinsic::x86_sse2_sub_sd: case Intrinsic::x86_sse2_sub_sd:
TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS, TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS,
II->getName()), *II); II->getName()), *II);
break; break;
case Intrinsic::x86_sse_mul_ss: case Intrinsic::x86_sse_mul_ss:
case Intrinsic::x86_sse2_mul_sd: case Intrinsic::x86_sse2_mul_sd:
TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS, TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS,
II->getName()), *II); II->getName()), *II);
break; break;
} }
Instruction *New = Instruction *New =
InsertElementInst::Create( InsertElementInst::Create(
UndefValue::get(II->getType()), TmpV, UndefValue::get(II->getType()), TmpV,
ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false), ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false),
II->getName()); II->getName());
InsertNewInstWith(New, *II); InsertNewInstWith(New, *II);
return New; return New;
} }
} }
// If lowest element of a scalar op isn't used then use Arg0.
if (DemandedElts.getLoBits(1) != 1)
return II->getArgOperand(0);
// Output elements are undefined if both are undefined. Consider things // Output elements are undefined if both are undefined. Consider things
// like undef&0. The result is known zero, not undef. // like undef&0. The result is known zero, not undef.
UndefElts &= UndefElts2; UndefElts &= UndefElts2;
break; break;
// SSE4A instructions leave the upper 64-bits of the 128-bit result // SSE4A instructions leave the upper 64-bits of the 128-bit result
// in an undefined state. // in an undefined state.
case Intrinsic::x86_sse4a_extrq: case Intrinsic::x86_sse4a_extrq:
Show All 11 Lines

llvm/trunk/test/Transforms/InstCombine/x86-sse.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s ; RUN: opt < %s -instcombine -S | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define float @test_rcp_ss_0(float %a) { define float @test_rcp_ss_0(float %a) {
; CHECK-LABEL: @test_rcp_ss_0( ; CHECK-LABEL: @test_rcp_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3 ; CHECK-NEXT: ret float [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 0
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 0 %6 = extractelement <4 x float> %5, i32 0
ret float %6 ret float %6
} }
define float @test_rcp_ss_1(float %a) { define float @test_rcp_ss_1(float %a) {
; CHECK-LABEL: @test_rcp_ss_1( ; CHECK-LABEL: @test_rcp_ss_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 1
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 1 %6 = extractelement <4 x float> %5, i32 1
ret float %6 ret float %6
} }
define float @test_sqrt_ss_0(float %a) { define float @test_sqrt_ss_0(float %a) {
; CHECK-LABEL: @test_sqrt_ss_0( ; CHECK-LABEL: @test_sqrt_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3 ; CHECK-NEXT: ret float [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 0
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 0 %6 = extractelement <4 x float> %5, i32 0
ret float %6 ret float %6
} }
define float @test_sqrt_ss_2(float %a) { define float @test_sqrt_ss_2(float %a) {
; CHECK-LABEL: @test_sqrt_ss_2( ; CHECK-LABEL: @test_sqrt_ss_2(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 2.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 2
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 2 %6 = extractelement <4 x float> %5, i32 2
ret float %6 ret float %6
} }
define float @test_rsqrt_ss_0(float %a) { define float @test_rsqrt_ss_0(float %a) {
; CHECK-LABEL: @test_rsqrt_ss_0( ; CHECK-LABEL: @test_rsqrt_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3 ; CHECK-NEXT: ret float [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 0
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 0 %6 = extractelement <4 x float> %5, i32 0
ret float %6 ret float %6
} }
define float @test_rsqrt_ss_3(float %a) { define float @test_rsqrt_ss_3(float %a) {
; CHECK-LABEL: @test_rsqrt_ss_3( ; CHECK-LABEL: @test_rsqrt_ss_3(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 3.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 3
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 3 %6 = extractelement <4 x float> %5, i32 3
ret float %6 ret float %6
} }
define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: @test_add_ss( ; CHECK-LABEL: @test_add_ss(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a, <4 x float> %b) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a, <4 x float> %b)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a, <4 x float> %3) %4 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a, <4 x float> %3)
ret <4 x float> %4 ret <4 x float> %4
} }
define float @test_add_ss_0(float %a, float %b) { define float @test_add_ss_0(float %a, float %b) {
; CHECK-LABEL: @test_add_ss_0( ; CHECK-LABEL: @test_add_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = fadd float %a, %b
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: ret float [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
; CHECK-NEXT: ret float [[R]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
%7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %8) %9 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %8)
%r = extractelement <4 x float> %9, i32 0 %r = extractelement <4 x float> %9, i32 0
ret float %r ret float %r
} }
define float @test_add_ss_1(float %a, float %b) { define float @test_add_ss_1(float %a, float %b) {
; CHECK-LABEL: @test_add_ss_1( ; CHECK-LABEL: @test_add_ss_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP6]], i32 1
; CHECK-NEXT: ret float [[TMP7]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %5) %6 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %5)
%7 = extractelement <4 x float> %6, i32 1 %7 = extractelement <4 x float> %6, i32 1
Show All 27 Lines;
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %8) %9 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %8)
%r = extractelement <4 x float> %9, i32 0 %r = extractelement <4 x float> %9, i32 0
ret float %r ret float %r
} }
define float @test_sub_ss_2(float %a, float %b) { define float @test_sub_ss_2(float %a, float %b) {
; CHECK-LABEL: @test_sub_ss_2( ; CHECK-LABEL: @test_sub_ss_2(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> <float undef, float undef, float 2.000000e+00, float undef>, <4 x float> undef) ; CHECK-NEXT: ret float 2.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
; CHECK-NEXT: ret float [[TMP2]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %5) %6 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %5)
%7 = extractelement <4 x float> %6, i32 2 %7 = extractelement <4 x float> %6, i32 2
Show All 27 Lines;
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %8) %9 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %8)
%r = extractelement <4 x float> %9, i32 0 %r = extractelement <4 x float> %9, i32 0
ret float %r ret float %r
} }
define float @test_mul_ss_3(float %a, float %b) { define float @test_mul_ss_3(float %a, float %b) {
; CHECK-LABEL: @test_mul_ss_3( ; CHECK-LABEL: @test_mul_ss_3(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> <float undef, float undef, float undef, float 3.000000e+00>, <4 x float> undef) ; CHECK-NEXT: ret float 3.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
; CHECK-NEXT: ret float [[TMP2]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %5) %6 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %5)
%7 = extractelement <4 x float> %6, i32 3 %7 = extractelement <4 x float> %6, i32 3
Show All 10 Lines;
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a, <4 x float> %3) %4 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a, <4 x float> %3)
ret <4 x float> %4 ret <4 x float> %4
} }
define float @test_div_ss_0(float %a, float %b) { define float @test_div_ss_0(float %a, float %b) {
; CHECK-LABEL: @test_div_ss_0( ; CHECK-LABEL: @test_div_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2 ; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3 ; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
; CHECK-NEXT: ret float [[R]] ; CHECK-NEXT: ret float [[R]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
%7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %8) %9 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %8)
%r = extractelement <4 x float> %9, i32 0 %r = extractelement <4 x float> %9, i32 0
ret float %r ret float %r
} }
define float @test_div_ss_1(float %a, float %b) { define float @test_div_ss_1(float %a, float %b) {
; CHECK-LABEL: @test_div_ss_1( ; CHECK-LABEL: @test_div_ss_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP6]], i32 1
; CHECK-NEXT: ret float [[TMP7]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %5) %6 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %5)
%7 = extractelement <4 x float> %6, i32 1 %7 = extractelement <4 x float> %6, i32 1
Show All 30 Lines;
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %8) %9 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %8)
%10 = extractelement <4 x float> %9, i32 0 %10 = extractelement <4 x float> %9, i32 0
ret float %10 ret float %10
} }
define float @test_min_ss_2(float %a, float %b) { define float @test_min_ss_2(float %a, float %b) {
; CHECK-LABEL: @test_min_ss_2( ; CHECK-LABEL: @test_min_ss_2(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float undef, float undef, float 2.000000e+00, float undef>, <4 x float> undef) ; CHECK-NEXT: ret float 2.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
; CHECK-NEXT: ret float [[TMP2]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %5) %6 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %5)
%7 = extractelement <4 x float> %6, i32 2 %7 = extractelement <4 x float> %6, i32 2
Show All 30 Lines;
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %8) %9 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %8)
%10 = extractelement <4 x float> %9, i32 0 %10 = extractelement <4 x float> %9, i32 0
ret float %10 ret float %10
} }
define float @test_max_ss_3(float %a, float %b) { define float @test_max_ss_3(float %a, float %b) {
; CHECK-LABEL: @test_max_ss_3( ; CHECK-LABEL: @test_max_ss_3(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> <float undef, float undef, float undef, float 3.000000e+00>, <4 x float> undef) ; CHECK-NEXT: ret float 3.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
; CHECK-NEXT: ret float [[TMP2]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %5) %6 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %5)
%7 = extractelement <4 x float> %6, i32 3 %7 = extractelement <4 x float> %6, i32 3
Show All 10 Lines;
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a, <4 x float> %3, i8 0) %4 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a, <4 x float> %3, i8 0)
ret <4 x float> %4 ret <4 x float> %4
} }
define float @test_cmp_ss_0(float %a, float %b) { define float @test_cmp_ss_0(float %a, float %b) {
; CHECK-LABEL: @test_cmp_ss_0( ; CHECK-LABEL: @test_cmp_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2 ; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]], i8 0)
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3 ; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP4]], <4 x float> [[TMP5]], i8 0)
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP6]], i32 0
; CHECK-NEXT: ret float [[R]] ; CHECK-NEXT: ret float [[R]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
%7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %8, i8 0) %9 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %8, i8 0)
%r = extractelement <4 x float> %9, i32 0 %r = extractelement <4 x float> %9, i32 0
ret float %r ret float %r
} }
define float @test_cmp_ss_1(float %a, float %b) { define float @test_cmp_ss_1(float %a, float %b) {
; CHECK-LABEL: @test_cmp_ss_1( ; CHECK-LABEL: @test_cmp_ss_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP6:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP4]], <4 x float> [[TMP5]], i8 0)
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP6]], i32 1
; CHECK-NEXT: ret float [[TMP7]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %5, i8 0) %6 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %5, i8 0)
%7 = extractelement <4 x float> %6, i32 1 %7 = extractelement <4 x float> %6, i32 1
▲ Show 20 Lines • Show All 256 Lines • Show Last 20 Lines

llvm/trunk/test/Transforms/InstCombine/x86-sse2.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s ; RUN: opt < %s -instcombine -S | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define double @test_sqrt_sd_0(double %a) { define double @test_sqrt_sd_0(double %a) {
; CHECK-LABEL: @test_sqrt_sd_0( ; CHECK-LABEL: @test_sqrt_sd_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 ; CHECK-NEXT: ret double [[TMP3]]
; CHECK-NEXT: ret double [[TMP4]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2) %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
%4 = extractelement <2 x double> %3, i32 0 %4 = extractelement <2 x double> %3, i32 0
ret double %4 ret double %4
} }
define double @test_sqrt_sd_1(double %a) { define double @test_sqrt_sd_1(double %a) {
; CHECK-LABEL: @test_sqrt_sd_1( ; CHECK-LABEL: @test_sqrt_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
; CHECK-NEXT: ret double [[TMP4]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2) %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
%4 = extractelement <2 x double> %3, i32 1 %4 = extractelement <2 x double> %3, i32 1
ret double %4 ret double %4
} }
define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test_add_sd( ; CHECK-LABEL: @test_add_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x double> %b) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x double> %b)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x double> %1) %2 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %a, <2 x double> %1)
ret <2 x double> %2 ret <2 x double> %2
} }
define double @test_add_sd_0(double %a, double %b) { define double @test_add_sd_0(double %a, double %b) {
; CHECK-LABEL: @test_add_sd_0( ; CHECK-LABEL: @test_add_sd_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = fadd double %a, %b
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1 ; CHECK-NEXT: ret double [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> [[TMP2]], <2 x double> [[TMP3]])
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
; CHECK-NEXT: ret double [[TMP5]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_add_sd_1(double %a, double %b) { define double @test_add_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_add_sd_1( ; CHECK-LABEL: @test_add_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> [[TMP2]], <2 x double> [[TMP3]])
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
; CHECK-NEXT: ret double [[TMP5]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
Show All 20 Lines;
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_sub_sd_1(double %a, double %b) { define double @test_sub_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_sub_sd_1( ; CHECK-LABEL: @test_sub_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> <double undef, double 1.000000e+00>, <2 x double> undef) ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
; CHECK-NEXT: ret double [[TMP2]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
Show All 20 Lines;
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_mul_sd_1(double %a, double %b) { define double @test_mul_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_mul_sd_1( ; CHECK-LABEL: @test_mul_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> <double undef, double 1.000000e+00>, <2 x double> undef) ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
; CHECK-NEXT: ret double [[TMP2]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
} }
define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test_div_sd( ; CHECK-LABEL: @test_div_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a, <2 x double> %b) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a, <2 x double> %b)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a, <2 x double> %1) %2 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %a, <2 x double> %1)
ret <2 x double> %2 ret <2 x double> %2
} }
define double @test_div_sd_0(double %a, double %b) { define double @test_div_sd_0(double %a, double %b) {
; CHECK-LABEL: @test_div_sd_0( ; CHECK-LABEL: @test_div_sd_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> undef, double %b, i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> [[TMP2]], <2 x double> [[TMP3]]) ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 ; CHECK-NEXT: ret double [[TMP4]]
; CHECK-NEXT: ret double [[TMP5]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_div_sd_1(double %a, double %b) { define double @test_div_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_div_sd_1( ; CHECK-LABEL: @test_div_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> [[TMP2]], <2 x double> [[TMP3]])
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
; CHECK-NEXT: ret double [[TMP5]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
Show All 23 Lines;
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_min_sd_1(double %a, double %b) { define double @test_min_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_min_sd_1( ; CHECK-LABEL: @test_min_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> <double undef, double 1.000000e+00>, <2 x double> undef) ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
; CHECK-NEXT: ret double [[TMP2]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
Show All 23 Lines;
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_max_sd_1(double %a, double %b) { define double @test_max_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_max_sd_1( ; CHECK-LABEL: @test_max_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> <double undef, double 1.000000e+00>, <2 x double> undef) ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
; CHECK-NEXT: ret double [[TMP2]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
} }
define <2 x double> @test_cmp_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_cmp_sd(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test_cmp_sd( ; CHECK-LABEL: @test_cmp_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a, <2 x double> %b, i8 0) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a, <2 x double> %b, i8 0)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a, <2 x double> %1, i8 0) %2 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a, <2 x double> %1, i8 0)
ret <2 x double> %2 ret <2 x double> %2
} }
define double @test_cmp_sd_0(double %a, double %b) { define double @test_cmp_sd_0(double %a, double %b) {
; CHECK-LABEL: @test_cmp_sd_0( ; CHECK-LABEL: @test_cmp_sd_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> undef, double %b, i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]], i8 0)
; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP2]], <2 x double> [[TMP3]], i8 0) ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 ; CHECK-NEXT: ret double [[TMP4]]
; CHECK-NEXT: ret double [[TMP5]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0) %5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_cmp_sd_1(double %a, double %b) { define double @test_cmp_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_cmp_sd_1( ; CHECK-LABEL: @test_cmp_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP2]], <2 x double> [[TMP3]], i8 0)
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 1
; CHECK-NEXT: ret double [[TMP5]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0) %5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines

llvm/trunk/test/Transforms/InstCombine/x86-sse41.ll

Show All 10 Lines;
%2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1 %2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
%3 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %1, <2 x double> %2, i32 10) %3 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %1, <2 x double> %2, i32 10)
ret <2 x double> %3 ret <2 x double> %3
} }
define double @test_round_sd_0(double %a, double %b) { define double @test_round_sd_0(double %a, double %b) {
; CHECK-LABEL: @test_round_sd_0( ; CHECK-LABEL: @test_round_sd_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %b, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %b, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> <double undef, double 1.000000e+00>, <2 x double> [[TMP1]], i32 10) ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> undef, <2 x double> [[TMP1]], i32 10)
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
; CHECK-NEXT: ret double [[TMP3]] ; CHECK-NEXT: ret double [[TMP3]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %2, <2 x double> %4, i32 10) %5 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %2, <2 x double> %4, i32 10)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
ret double %6 ret double %6
} }
define double @test_round_sd_1(double %a, double %b) { define double @test_round_sd_1(double %a, double %b) {
; CHECK-LABEL: @test_round_sd_1( ; CHECK-LABEL: @test_round_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %b, i32 0 ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> <double undef, double 1.000000e+00>, <2 x double> [[TMP1]], i32 10)
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 1
; CHECK-NEXT: ret double [[TMP3]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = insertelement <2 x double> undef, double %b, i32 0 %3 = insertelement <2 x double> undef, double %b, i32 0
%4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1 %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
%5 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %2, <2 x double> %4, i32 10) %5 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %2, <2 x double> %4, i32 10)
%6 = extractelement <2 x double> %5, i32 1 %6 = extractelement <2 x double> %5, i32 1
ret double %6 ret double %6
Show All 12 Lines;
%6 = insertelement <4 x float> %5, float 3.000000e+00, i32 3 %6 = insertelement <4 x float> %5, float 3.000000e+00, i32 3
%7 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %3, <4 x float> %6, i32 10) %7 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %3, <4 x float> %6, i32 10)
ret <4 x float> %7 ret <4 x float> %7
} }
define float @test_round_ss_0(float %a, float %b) { define float @test_round_ss_0(float %a, float %b) {
; CHECK-LABEL: @test_round_ss_0( ; CHECK-LABEL: @test_round_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %b, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %b, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, <4 x float> [[TMP1]], i32 10) ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> undef, <4 x float> [[TMP1]], i32 10)
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP2]], i32 0 ; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
; CHECK-NEXT: ret float [[R]] ; CHECK-NEXT: ret float [[R]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
%7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %4, <4 x float> %8, i32 10) %9 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %4, <4 x float> %8, i32 10)
%r = extractelement <4 x float> %9, i32 0 %r = extractelement <4 x float> %9, i32 0
ret float %r ret float %r
} }
define float @test_round_ss_2(float %a, float %b) { define float @test_round_ss_2(float %a, float %b) {
; CHECK-LABEL: @test_round_ss_2( ; CHECK-LABEL: @test_round_ss_2(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %b, i32 0 ; CHECK-NEXT: ret float 2.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, <4 x float> [[TMP1]], i32 10)
; CHECK-NEXT: [[R:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
; CHECK-NEXT: ret float [[R]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = insertelement <4 x float> undef, float %b, i32 0 %5 = insertelement <4 x float> undef, float %b, i32 0
%6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1 %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
%7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2 %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
%8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3 %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
%9 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %4, <4 x float> %8, i32 10) %9 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %4, <4 x float> %8, i32 10)
%r = extractelement <4 x float> %9, i32 2 %r = extractelement <4 x float> %9, i32 2
ret float %r ret float %r
} }
declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone

llvm/trunk/test/Transforms/InstCombine/x86-xop.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s ; RUN: opt < %s -instcombine -S | FileCheck %s
define double @test_vfrcz_sd_0(double %a) { define double @test_vfrcz_sd_0(double %a) {
; CHECK-LABEL: @test_vfrcz_sd_0( ; CHECK-LABEL: @test_vfrcz_sd_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 ; CHECK-NEXT: ret double [[TMP3]]
; CHECK-NEXT: ret double [[TMP4]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2) %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
%4 = extractelement <2 x double> %3, i32 0 %4 = extractelement <2 x double> %3, i32 0
ret double %4 ret double %4
} }
define double @test_vfrcz_sd_1(double %a) { define double @test_vfrcz_sd_1(double %a) {
; CHECK-LABEL: @test_vfrcz_sd_1( ; CHECK-LABEL: @test_vfrcz_sd_1(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double %a, i32 0 ; CHECK-NEXT: ret double 1.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 1
; CHECK-NEXT: ret double [[TMP4]]
; ;
%1 = insertelement <2 x double> undef, double %a, i32 0 %1 = insertelement <2 x double> undef, double %a, i32 0
%2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1 %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
%3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2) %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
%4 = extractelement <2 x double> %3, i32 1 %4 = extractelement <2 x double> %3, i32 1
ret double %4 ret double %4
} }
define float @test_vfrcz_ss_0(float %a) { define float @test_vfrcz_ss_0(float %a) {
; CHECK-LABEL: @test_vfrcz_ss_0( ; CHECK-LABEL: @test_vfrcz_ss_0(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3 ; CHECK-NEXT: ret float [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 0
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 0 %6 = extractelement <4 x float> %5, i32 0
ret float %6 ret float %6
} }
define float @test_vfrcz_ss_3(float %a) { define float @test_vfrcz_ss_3(float %a) {
; CHECK-LABEL: @test_vfrcz_ss_3( ; CHECK-LABEL: @test_vfrcz_ss_3(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0 ; CHECK-NEXT: ret float 3.000000e+00
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float 1.000000e+00, i32 1
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> [[TMP2]], float 2.000000e+00, i32 2
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> [[TMP3]], float 3.000000e+00, i32 3
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 3
; CHECK-NEXT: ret float [[TMP6]]
; ;
%1 = insertelement <4 x float> undef, float %a, i32 0 %1 = insertelement <4 x float> undef, float %a, i32 0
%2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
%3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
%4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
%5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4) %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
%6 = extractelement <4 x float> %5, i32 3 %6 = extractelement <4 x float> %5, i32 3
ret float %6 ret float %6
▲ Show 20 Lines • Show All 228 Lines • Show Last 20 Lines