Fix typing on generated LXV2DX/STXV2DX instructions

[niravd]

Summary

[PPC] Previously when casting generic loads to LXV2DX/ST instructions we
would leave the original load return type in place allowing for an
assertion failure when we merge two equivalent LXV2DX nodes with
different types.

This fixes PR27350.

[mcrosier]

Testcase?

[nemanjai]

Just one inline comment (actually a question for my understanding) and pending a test case, this LGTM. Perhaps @wschmidt would like to take a look as well.
I have also tested the patch with a double bootstrap build and it all works fine.

lib/Target/PowerPC/PPCISelLowering.cpp

10368 ↗

(On Diff #53792)

Pardon my ignorance here, I just don't follow why we're adding this ISD::MERGE_VALUES node here.

[wschmidt]

In D19133#402129, @nemanjai wrote:

Just one inline comment (actually a question for my understanding) and pending a test case, this LGTM. Perhaps @wschmidt would like to take a look as well.

I have nothing to add to that -- I am also unsure what that is for.

[niravd]

Added cleaned up testcase

lib/Target/PowerPC/PPCISelLowering.cpp

10368 ↗

(On Diff #53792)

Merge Value is an identity node that returns its inputs and is used to work around the fact that node replacements do not always result in a final node with constructing all the values in the correct way. Here replacing the load with a different load and a swap node was fine because they returned the same shape output (value, chain), but with the bitcast we need to make a new ephemeral node to hold the bitcast result and the swap node's chain value.

[wschmidt]

lib/Target/PowerPC/PPCISelLowering.cpp

10368 ↗

(On Diff #53877)

Ah, OK, that makes sense. Perhaps add a short comment to that effect? This is uncommon enough that it will probably raise questions in the future as well.

[niravd]

Add comment

[wschmidt]

Thanks. This LGTM!

[gabbayo]

This patch causes a regression in mesa's llvmpipe driver.
The regression is detected by running piglit test suite.
The following two tests fail with this patch (and pass without it):

fbo-blending-formats GL_EXT_texture_snorm -auto -fbo
max-samplers border -auto -fbo

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

case ISD::INTRINSIC_W_CHAIN: {
     MMO = Intrin->getMemOperand();
     break;
   }
   }
 
   MVT VecTy = N->getValueType(0).getSimpleVT();
   SDValue LoadOps[] = { Chain, Base };
   SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
-                                         DAG.getVTList(VecTy, MVT::Other),
-                                         LoadOps, VecTy, MMO);
+                                         DAG.getVTList(MVT::v2f64, MVT::Other),
+                                         LoadOps, MVT::v2f64, MMO);
+
   DCI.AddToWorklist(Load.getNode());
   Chain = Load.getValue(1);
-  SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
-                             DAG.getVTList(VecTy, MVT::Other), Chain, Load);
+  SDValue Swap = DAG.getNode(
+      PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load);
   DCI.AddToWorklist(Swap.getNode());
+
+  // Add a bitcast if the resulting load type doesn't match v2f64.
+  if (VecTy != MVT::v2f64) {
+    SDValue N = DAG.getNode(ISD::BITCAST, dl, VecTy, Swap);
+    DCI.AddToWorklist(N.getNode());
+    // Package {bitcast value, swap's chain} to match Load's shape.
+    return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
+                       N, Swap.getValue(1));
+  }
+
   return Swap;
 }
 
 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
 // builtins) into stores with swaps.
 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
case ISD::INTRINSIC_VOID: {
     MMO = Intrin->getMemOperand();
     SrcOpnd = 2;
     break;
   }
   }
 
   SDValue Src = N->getOperand(SrcOpnd);
   MVT VecTy = Src.getValueType().getSimpleVT();
+
+  // All stores are done as v2f64 and possible bit cast.
+  if (VecTy != MVT::v2f64) {
+    Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src);
+    DCI.AddToWorklist(Src.getNode());
+  }
+
   SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
-                             DAG.getVTList(VecTy, MVT::Other), Chain, Src);
+                             DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src);
   DCI.AddToWorklist(Swap.getNode());
   Chain = Swap.getValue(1);
   SDValue StoreOps[] = { Chain, Swap, Base };
   SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
                                           DAG.getVTList(MVT::Other),
                                           StoreOps, VecTy, MMO);
   DCI.AddToWorklist(Store.getNode());
   return Store;

llvm/trunk/test/CodeGen/PowerPC/pr27350.ll

+; RUN: llc -mcpu=ppc64le -mtriple=powerpc64le-unknown-linux-gnu < %s
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
+
+; Function Attrs: nounwind
+define internal fastcc void @foo() unnamed_addr #1 align 2 {
+entry:
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 16, i32 8, i1 false)
+  %0 = load <2 x i64>, <2 x i64>* null, align 8
+  %1 = extractelement <2 x i64> %0, i32 1
+  %.fca.1.insert159.i = insertvalue [2 x i64] undef, i64 %1, 1
+  tail call fastcc void @bar([2 x i64] undef, [2 x i64] %.fca.1.insert159.i) #2
+  unreachable
+}
+
+; Function Attrs: nounwind
+declare fastcc void @bar([2 x i64], [2 x i64]) unnamed_addr #1 align 2
+
+attributes #0 = { argmemonly nounwind }
+attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.9.0 (trunk) (llvm/trunk 266222)"}