AMDGPU: Correct reported code size

[arsenm]

Summary

For a while this has been counting many instructions as 0,
so the printed code size comment hasn't been very meaningful.

This sets the instruction size to 8 for all 64-bit instructions.
For instructions which may include an additional 4 byte literal,
it is set to 0 because the size must be determined from the operands.

This currently breaks the disassembler for all of the 4-byte
instructions which may have a literal.

[vpykhtin]

Why not to consider 4 byte instructions as having potentially larger size and keep current encoding sizes?

[arsenm]

In D19132#401791, @vpykhtin wrote:

Why not to consider 4 byte instructions as having potentially larger size and keep current encoding sizes?

It's supposed to be 0 if it can't be determined just from the opcode:

// Size - Size of encoded instruction, or zero if the size cannot be determined
// from the opcode.
int Size = 0;

[vpykhtin]

I'm ok with the change but I need to find out which disassembly decoding table zero sized instructions will be placed to or is there other decoding mechanism for such instructions.

[SamWot]

LGTM

[arsenm]

Can you take a look at what is required to fix the disassembler with this patch?

[arsenm]

I've split the function into r271936 and left the rest until the disassembler is fixed

[vpykhtin]

In D19132#450151, @arsenm wrote:

I've split the function into r271936 and left the rest until the disassembler is fixed

can you show the diff?

Sorry, I completely forgot about this patch, I'll try to take a look what it takes to fix disasm today or tommorow.

[arsenm]

Update diff and drop already committed parts

[arsenm]

Update diff

[vpykhtin]

In D19132#401815, @arsenm wrote:

In D19132#401791, @vpykhtin wrote:

Why not to consider 4 byte instructions as having potentially larger size and keep current encoding sizes?

It's supposed to be 0 if it can't be determined just from the opcode:

// Size - Size of encoded instruction, or zero if the size cannot be determined
// from the opcode.
int Size = 0;

It turns out when Size==0 no decoding code is generated for an instruction at all. See FixedLenDecoderEmitter.cpp, line 2276. The comment above probably assumes custom decoder should be used but this is an overkill in this situation. I think we should left current sizes and fix computed len somehow differently.

[arsenm]

Committed a bit more of the patch in r283437

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 #include "AMDGPUSubtarget.h"
 #include "R600Defines.h"
 #include "R600MachineFunctionInfo.h"
 #include "R600RegisterInfo.h"
 #include "SIDefines.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIInstrInfo.h"
 #include "SIRegisterInfo.h"
+#include "SIInstrInfo.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
       // TODO: CodeSize should account for multiple functions.
 
       // TODO: Should we count size of debug info?
       if (MI.isDebugValue())
         continue;
 
+      if (isVerbose())
         CodeSize += TII->getInstSizeInBytes(MI);
 
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
         const MachineOperand &MO = MI.getOperand(op_idx);
         unsigned width = 0;
         bool isSGPR = false;
 
         if (!MO.isReg())

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
 
   uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   unsigned bytes = Desc.getSize();
 
+  // Instructions sizes that can't just be determined by the opcode have a base
+  // size of 4, and then the following 4 byte literal.
+  if (bytes == 0)
+    bytes = 4;
+
   for (unsigned i = 0; i < bytes; i++) {
     OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
   }
 
   if (bytes > 4)
     return;
 
   // Check for additional literals in SRC0/1/2 (Op 1/2/3)
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
   }
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   if (isSrcOperand(Desc, OpNo)) {
     int RCID = Desc.OpInfo[OpNo].RegClass;
     const MCRegisterClass &RC = MRI.getRegClass(RCID);
 
     uint32_t Enc = getLitEncoding(MO, RC.getSize());
-    if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
+    if (Enc != ~0U && (Enc != 255 || Desc.getSize() != 8))
       return Enc;
 
   } else if (MO.isImm())
     return MO.getImm();
 
   llvm_unreachable("Encoding of this operand type is not supported yet.");
   return 0;
 }
 

lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
 
   let SchedRW = [Write32Bit];
 
   field bits<1> DisableSIDecoder = 0;
   field bits<1> DisableVIDecoder = 0;
   field bits<1> DisableDecoder = 0;
 
   let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
+
+  // Similar to Size field. Get encoding size for the format ignoring
+  // 32-bit literals that could really make the full instruction
+  // encoding be 8 bytes.
+  int BaseSize = 4;
 }
 
 class Enc32 {
   field bits<32> Inst;
-  int Size = 4;
 }
 
 class Enc64 {
   field bits<64> Inst;
-  int Size = 8;
 }
 
 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
 
 let Uses = [EXEC] in {
 
 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
class VOPCCommon <dag ins, string asm, list<dag> pattern> :
   let Size = 4;
   let Defs = [VCC];
 }
 
 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
     VOPAnyCommon <outs, ins, asm, pattern> {
 
   let VOP1 = 1;
-  let Size = 4;
 }
 
 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
     VOPAnyCommon <outs, ins, asm, pattern> {
 
   let VOP2 = 1;
-  let Size = 4;
 }
 
 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0, bit VOP3Only = 0> :
     VOPAnyCommon <outs, ins, asm, pattern> {
 
   // Using complex patterns gives VOP3 patterns a very high complexity rating,
   // but standalone patterns are almost always prefered, so we need to adjust the
   // priority lower.  The goal is to use a high number to reduce complexity to
   // zero (or less than zero).
   let AddedComplexity = -1000;
 
   let VOP3 = 1;
   let VALU = 1;
 
   let AsmMatchConverter =
     !if(!eq(VOP3Only,1),
         "cvtVOP3",
         !if(!eq(HasMods,1), "cvtVOP3_2_mod", ""));
 
   let isCodeGenOnly = 0;
 
-  int Size = 8;
+  let Size = 8;
+  let BaseSize = 8;
 
   // Because SGPRs may be allowed if there are multiple operands, we
   // need a post-isel hook to insert copies in order to avoid
   // violating constant bus requirements.
   let hasPostISelHook = 1;
 }
 
 } // End Uses = [EXEC]

 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
     InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
 
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let SALU = 1;
   let SOPP = 1;
+  let Size = 4;
 
   let UseNamedOperandTable = 1;
 }
 
 } // let SchedRW = [WriteSALU]
 
 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI<outs, ins, asm, pattern> {
 
   let LGKM_CNT = 1;
   let SMRD = 1;
+
   let mayStore = 0;
   let mayLoad = 1;
   let hasSideEffects = 0;
   let UseNamedOperandTable = 1;
   let SchedRW = [WriteSMEM];
 }
 
 //===----------------------------------------------------------------------===//

 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
     VOPCCommon <ins, asm, pattern>, VOPCe <op>;
 
 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
   let mayLoad = 1;
   let mayStore = 0;
   let hasSideEffects = 0;
+  let Size = 4;
 }
 
 } // End Uses = [EXEC]
 
 //===----------------------------------------------------------------------===//
 // Vector I/O operations
 //===----------------------------------------------------------------------===//
 
 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
 
   let LGKM_CNT = 1;
   let DS = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let UseNamedOperandTable = 1;
   let Uses = [M0, EXEC];
 
   // Most instruction load and store data, so set this as the default.
   let mayLoad = 1;
   let mayStore = 1;
 
   let hasSideEffects = 0;
   let AsmMatchConverter = "cvtDS";
   let SchedRW = [WriteLDS];
 }
 
 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI<outs, ins, asm, pattern> {
 
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MUBUF = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let Uses = [EXEC];
 
   let hasSideEffects = 0;
   let UseNamedOperandTable = 1;
   let AsmMatchConverter = "cvtMubuf";
   let SchedRW = [WriteVMEM];
 }
 
 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI<outs, ins, asm, pattern> {
 
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MTBUF = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let Uses = [EXEC];
 
   let hasSideEffects = 0;
   let UseNamedOperandTable = 1;
   let SchedRW = [WriteVMEM];
 }
 
 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI<outs, ins, asm, pattern>, FLATe <op> {
   let FLAT = 1;
   // Internally, FLAT instruction are executed as both an LDS and a
   // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
   // and are not considered done until both have been decremented.
   let VM_CNT = 1;
   let LGKM_CNT = 1;
+  let Size = 8;
+  let BaseSize = 8;
 
   let Uses = [EXEC, FLAT_SCR]; // M0
 
   let UseNamedOperandTable = 1;
   let hasSideEffects = 0;
   let SchedRW = [WriteVMEM];
 }
 
 class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
     InstSI <outs, ins, asm, pattern> {
 
   let VM_CNT = 1;
   let EXP_CNT = 1;
   let MIMG = 1;
+  let Size = 8;
+  let BaseSize = 8;
   let Uses = [EXEC];
 
   let UseNamedOperandTable = 1;
   let hasSideEffects = 0; // XXX ????
 }

lib/Target/AMDGPU/SIInstrInfo.td

 class EXPCommon : InstSI<
   (outs),
   (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
        VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
   "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
   [] > {
 
   let EXP_CNT = 1;
+  let Size = 8;
   let Uses = [EXEC];
   let SchedRW = [WriteExport];
 }
 
 multiclass EXP_m {
 
   let isPseudo = 1, isCodeGenOnly = 1 in {
     def "" : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.NONE> ;
multiclass SOP1_64_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
     opName#" $sdst, $src0", pattern
 >;
 
 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
   SOP2<outs, ins, "", pattern>,
   SIMCInstr<opName, SIEncodingFamily.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
-  let Size = 4;
 
   // Pseudo instructions have no encodings, but adding this field here allows
   // us to do:
   // let sdst = xxx in {
   // for multiclasses that include both real and pseudo instructions.
   field bits<7> sdst = 0;
 }
 
multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
 
   def _si : SOPK <outs, ins, asm, []>,
             SOPK64e <op.SI>,
             SIMCInstr<opName, SIEncodingFamily.SI> {
               let AssemblerPredicates = [isSICI];
               let DecoderNamespace = "SICI";
               let DisableDecoder = DisableSIDecoder;
               let isCodeGenOnly = 0;
+              let Size = 8;
             }
 
   def _vi : SOPK <outs, ins, asm, []>,
             SOPK64e <op.VI>,
             SIMCInstr<opName, SIEncodingFamily.VI> {
               let AssemblerPredicates = [isVI];
               let DecoderNamespace = "VI";
               let DisableDecoder = DisableVIDecoder;
               let isCodeGenOnly = 0;
+              let Size = 8;
             }
 }
 //===----------------------------------------------------------------------===//
 // SMRD classes
 //===----------------------------------------------------------------------===//
 
 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   SMRD <outs, ins, "", pattern>,
   SIMCInstr<opName, SIEncodingFamily.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins,
                         string asm> :
   SMRD <outs, ins, asm, []>,
   SMRD_IMMe <op>,
   SIMCInstr<opName, SIEncodingFamily.SI> {
   let AssemblerPredicates = [isSICI];
   let DecoderNamespace = "SICI";
   let DisableDecoder = DisableSIDecoder;
+  let Size = 4;
 }
 
 class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
                          string asm> :
   SMRD <outs, ins, asm, []>,
   SMRD_SOFFe <op>,
   SIMCInstr<opName, SIEncodingFamily.SI> {
   let AssemblerPredicates = [isSICI];
   let DecoderNamespace = "SICI";
   let DisableDecoder = DisableSIDecoder;
+  let Size = 4;
 }
 
 
 class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins,
                         string asm, list<dag> pattern = []> :
   SMRD <outs, ins, asm, pattern>,
   SMEM_IMMe_vi <op>,
   SIMCInstr<opName, SIEncodingFamily.VI> {
   let AssemblerPredicates = [isVI];
   let DecoderNamespace = "VI";
   let DisableDecoder = DisableVIDecoder;
+  let Size = 8;
 }
 
 class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
                          string asm, list<dag> pattern = []> :
   SMRD <outs, ins, asm, pattern>,
   SMEM_SOFFe_vi <op>,
   SIMCInstr<opName, SIEncodingFamily.VI> {
   let AssemblerPredicates = [isVI];
   let DecoderNamespace = "VI";
   let DisableDecoder = DisableVIDecoder;
+  let Size = 8;
 }
 
 
 multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins,
                    string asm, list<dag> pattern> {
 
   def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
 
defm _IMM : SMRD_IMM_m <
     opName#" $sdst, $sbase, $offset", []
   >;
 
   def _IMM_ci : SMRD <
     (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
     opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
     let AssemblerPredicates = [isCIOnly];
     let DecoderNamespace = "CI";
+    let Size = 8;
   }
 
   defm _SGPR : SMRD_SOFF_m <
     op, opName#"_SGPR", (outs dstClass:$sdst),
     (ins baseClass:$sbase, SReg_32:$soff),
     opName#" $sdst, $sbase, $soff", []
   >;
 }

 let isCodeGenOnly = 0 in {
   def _si : VOP2Common <P.Outs, P.Ins32,
                         !strconcat(opName, P.Asm32), []>,
             SIMCInstr <opName#"_e32", SIEncodingFamily.SI>,
             VOP2_MADKe <op.SI> {
             let AssemblerPredicates = [isSICI];
             let DecoderNamespace = "SICI";
             let DisableDecoder = DisableSIDecoder;
+            let Size = 8;
             }
 
   def _vi : VOP2Common <P.Outs, P.Ins32,
                         !strconcat(opName, P.Asm32), []>,
             SIMCInstr <opName#"_e32", SIEncodingFamily.VI>,
             VOP2_MADKe <op.VI> {
             let AssemblerPredicates = [isVI];
             let DecoderNamespace = "VI";
             let DisableDecoder = DisableVIDecoder;
+            let Size = 8;
             }
 } // End isCodeGenOnly = 0
 }
 
 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
   VOPCCommon <ins, "", pattern>,
   VOP <opName>,
   SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {

 //===----------------------------------------------------------------------===//
 // Vector instruction mappings
 //===----------------------------------------------------------------------===//
 
 // Maps an opcode in e32 form to its e64 equivalent
 def getVOPe64 : InstrMapping {
   let FilterClass = "VOP";
   let RowFields = ["OpName"];
-  let ColFields = ["Size"];
+  let ColFields = ["BaseSize"];
   let KeyCol = ["4"];
   let ValueCols = [["8"]];
 }
 
 // Maps an opcode in e64 form to its e32 equivalent
 def getVOPe32 : InstrMapping {
   let FilterClass = "VOP";
   let RowFields = ["OpName"];
-  let ColFields = ["Size"];
+  let ColFields = ["BaseSize"];
   let KeyCol = ["8"];
   let ValueCols = [["4"]];
 }
 
 def getMaskedMIMGOp : InstrMapping {
   let FilterClass = "MIMG_Mask";
   let RowFields = ["Op"];
   let ColFields = ["Channels"];

test/CodeGen/AMDGPU/hsa.ll

 ; On VI+ we also need to set MTYPE = 2
 ; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
 ; Make sure we generate flat store for HSA
 ; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
 
 ; HSA: .Lfunc_end0:
 ; HSA: .size   simple, .Lfunc_end0-simple
 
+; HSA-CI: codeLenInByte = 32{{$}}
+; HSA-VI: codeLenInByte = 36{{$}}
 define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
 entry:
   store i32 0, i32 addrspace(1)* %out
   ret void
 }