[mips] Enable IAS by default for 32-bit MIPS targets (O32).

[dsanders]

Summary

The MIPS IAS can now pass 'ninja check-all' and recurse now that the immediates
are all range checked properly.

Unfortunately we can't enable it by default for 64-bit targets yet since the N32
ABI is still very buggy and this also means we can't enable it for N64 either
because we can't distinguish between N32 and N64 in the relevant code.

The test changes reflect the formatting preferences of IAS as well as the way
that macro expansion occurs before the assembly text is emitted.

Depends on D18755, D18753

[vkalintiris]

LGTM.

[dsanders]

Thanks. Unfortunately, I'm going to have to hold off on committing this for a bit longer. I've found an interaction between IAS and inline assembly that causes -save-temps to change the behaviour of the code. We expand assembly macros before writing assembly text which causes expansions to happen twice when using -save-temps.

[dsanders]

It seems this didn't autoclose when I committed it.

lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp

MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
   CommentString               = "#";
   ZeroDirective               = "\t.space\t";
   GPRel32Directive            = "\t.gpword\t";
   GPRel64Directive            = "\t.gpdword\t";
   UseAssignmentForEHBegin = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   DwarfRegNumForCFI = true;
+
+  // Enable IAS by default for O32.
+  if (TheTriple.getArch() == Triple::mips ||
+      TheTriple.getArch() == Triple::mipsel)
+    UseIntegratedAssembler = true;
 }

test/CodeGen/Mips/hf16call32.ll

 ; stel: lui $25, %hi(v_df_df)
 ; stel: addiu $25, $25, %lo(v_df_df)
 ; stel: jr $25
 ; stel: .end __call_stub_fp_v_df_df
 
 declare float @sf_v() #1
 ; stel: .section .mips16.call.fp.sf_v,"ax",@progbits
 ; stel: .ent __call_stub_fp_sf_v
-; stel: move $18, $31
+; stel: move $18, $ra
 ; stel: jal sf_v
 ; stel: mfc1 $2, $f0
 ; stel: jr $18
 ; stel: .end __call_stub_fp_sf_v
 
 declare float @sf_sf(float) #1
 ; stel: .section .mips16.call.fp.sf_sf,"ax",@progbits
 ; stel: .ent __call_stub_fp_sf_sf

 ; stel: jal sf_df_df
 ; stel: mfc1 $2, $f0
 ; stel: jr $18
 ; stel: .end __call_stub_fp_sf_df_df
 
 declare double @df_v() #1
 ; stel: .section .mips16.call.fp.df_v,"ax",@progbits
 ; stel: .ent __call_stub_fp_df_v
-; stel: move $18, $31
+; stel: move $18, $ra
 ; stel: jal df_v
 ; stel: mfc1 $2, $f0
 ; stel: mfc1 $3, $f1
 ; stel: jr $18
 ; stel: .end __call_stub_fp_df_v
 
 declare double @df_sf(float) #1
 ; stel: .section .mips16.call.fp.df_sf,"ax",@progbits

 ; stel: mfc1 $2, $f0
 ; stel: mfc1 $3, $f1
 ; stel: jr $18
 ; stel: .end __call_stub_fp_df_df_df
 
 declare { float, float } @sc_v() #1
 ; stel: .section .mips16.call.fp.sc_v,"ax",@progbits
 ; stel: .ent __call_stub_fp_sc_v
-; stel: move $18, $31
+; stel: move $18, $ra
 ; stel: jal sc_v
 ; stel: mfc1 $2, $f0
 ; stel: mfc1 $3, $f2
 ; stel: jr $18
 ; stel: .end __call_stub_fp_sc_v
 
 declare { float, float } @sc_sf(float) #1
 ; stel: .section .mips16.call.fp.sc_sf,"ax",@progbits
 ; stel: .ent __call_stub_fp_sc_sf
 ; stel: mtc1 $4, $f12
 ; stel: move $18, ${{31|ra}}
 ; stel: jal sc_sf
 ; stel: mfc1 $2, $f0
 ; stel: mfc1 $3, $f2
 ; stel: jr $18
 ; stel: .end __call_stub_fp_sc_sf
 
 declare { double, double } @dc_v() #1
 ; stel: .section .mips16.call.fp.dc_v,"ax",@progbits
 ; stel: .ent __call_stub_fp_dc_v
-; stel: move $18, $31
+; stel: move $18, $ra
 ; stel: jal dc_v
 ; stel: mfc1 $4, $f2
 ; stel: mfc1 $5, $f3
 ; stel: mfc1 $2, $f0
 ; stel: mfc1 $3, $f1
 ; stel: jr $18
 ; stel: .end __call_stub_fp_dc_v
 

test/CodeGen/Mips/hf16call32_body.ll

entry:
   %p.addr = alloca float, align 4
   store float %p, float* %p.addr, align 4
   %0 = load float, float* %p.addr, align 4
   store float %0, float* @x, align 4
   ret void
 }
 ; stel: .section .mips16.fn.v_sf,"ax",@progbits
 ; stel: .ent __fn_stub_v_sf
-; stel: la $25, v_sf
+; stel: lui $25, %hi(v_sf)
+; stel: addiu $25, $25, %lo(v_sf)
 ; stel: mfc1 $4, $f12
 ; stel: jr $25
 ; stel: __fn_local_v_sf = v_sf
 ; stel: .end __fn_stub_v_sf
 
 declare i32 @printf(i8*, ...) #1
 
 ; Function Attrs: nounwind
 define void @v_df(double %p) #0 {
 entry:
   %p.addr = alloca double, align 8
   store double %p, double* %p.addr, align 8
   %0 = load double, double* %p.addr, align 8
   store double %0, double* @xd, align 8
   ret void
 }
 
 ; stel: .section .mips16.fn.v_df,"ax",@progbits
 ; stel: .ent __fn_stub_v_df
-; stel: la $25, v_df
+; stel: lui $25, %hi(v_df)
+; stel: addiu $25, $25, %lo(v_df)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f13
 ; stel: jr $25
 ; stel: __fn_local_v_df = v_df
 ; stel: .end __fn_stub_v_df
 
 ; Function Attrs: nounwind
 define void @v_sf_sf(float %p1, float %p2) #0 {
 entry:
   %p1.addr = alloca float, align 4
   %p2.addr = alloca float, align 4
   store float %p1, float* %p1.addr, align 4
   store float %p2, float* %p2.addr, align 4
   %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
   %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
   ret void
 }
 
 ; stel: .section .mips16.fn.v_sf_sf,"ax",@progbits
 ; stel: .ent __fn_stub_v_sf_sf
-; stel: la $25, v_sf_sf
+; stel: lui $25, %hi(v_sf_sf)
+; stel: addiu $25, $25, %lo(v_sf_sf)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f14
 ; stel: jr $25
 ; stel: __fn_local_v_sf_sf = v_sf_sf
 ; stel: .end __fn_stub_v_sf_sf
 
 ; Function Attrs: nounwind
 define void @v_sf_df(float %p1, double %p2) #0 {
 entry:
   %p1.addr = alloca float, align 4
   %p2.addr = alloca double, align 8
   store float %p1, float* %p1.addr, align 4
   store double %p2, double* %p2.addr, align 8
   %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
   %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
   ret void
 }
 
 ; stel: .section .mips16.fn.v_sf_df,"ax",@progbits
 ; stel: .ent __fn_stub_v_sf_df
-; stel: la $25, v_sf_df
+; stel: lui $25, %hi(v_sf_df)
+; stel: addiu $25, $25, %lo(v_sf_df)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $6, $f14
 ; stel: mfc1 $7, $f15
 ; stel: jr $25
 ; stel: __fn_local_v_sf_df = v_sf_df
 ; stel: .end __fn_stub_v_sf_df
 
 ; Function Attrs: nounwind
 define void @v_df_sf(double %p1, float %p2) #0 {
 entry:
   %p1.addr = alloca double, align 8
   %p2.addr = alloca float, align 4
   store double %p1, double* %p1.addr, align 8
   store float %p2, float* %p2.addr, align 4
   %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
   %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
   ret void
 }
 
 ; stel: .section .mips16.fn.v_df_sf,"ax",@progbits
 ; stel: .ent __fn_stub_v_df_sf
-; stel: la $25, v_df_sf
+; stel: lui $25, %hi(v_df_sf)
+; stel: addiu $25, $25, %lo(v_df_sf)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f13
 ; stel: mfc1 $6, $f14
 ; stel: jr $25
 ; stel: __fn_local_v_df_sf = v_df_sf
 ; stel: .end __fn_stub_v_df_sf
 
 ; Function Attrs: nounwind
 define void @v_df_df(double %p1, double %p2) #0 {
 entry:
   %p1.addr = alloca double, align 8
   %p2.addr = alloca double, align 8
   store double %p1, double* %p1.addr, align 8
   store double %p2, double* %p2.addr, align 8
   %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
   %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
   ret void
 }
 
 ; stel: .section .mips16.fn.v_df_df,"ax",@progbits
 ; stel: .ent __fn_stub_v_df_df
-; stel: la $25, v_df_df
+; stel: lui $25, %hi(v_df_df)
+; stel: addiu $25, $25, %lo(v_df_df)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f13
 ; stel: mfc1 $6, $f14
 ; stel: mfc1 $7, $f15
 ; stel: jr $25
 ; stel: __fn_local_v_df_df = v_df_df
 ; stel: .end __fn_stub_v_df_df
 
entry:
   store float %0, float* @x, align 4
   %1 = load float, float* @ret_sf, align 4
   ret float %1
 }
 
 
 ; stel: .section .mips16.fn.sf_sf,"ax",@progbits
 ; stel: .ent __fn_stub_sf_sf
-; stel: la $25, sf_sf
+; stel: lui $25, %hi(sf_sf)
+; stel: addiu $25, $25, %lo(sf_sf)
 ; stel: mfc1 $4, $f12
 ; stel: jr $25
 ; stel: __fn_local_sf_sf = sf_sf
 ; stel: .end __fn_stub_sf_sf
 
 
 ; Function Attrs: nounwind
 define float @sf_df(double %p) #0 {
 entry:
   %p.addr = alloca double, align 8
   store double %p, double* %p.addr, align 8
   %0 = load double, double* %p.addr, align 8
   store double %0, double* @xd, align 8
   %1 = load float, float* @ret_sf, align 4
   ret float %1
 }
 
 ; stel: .section .mips16.fn.sf_df,"ax",@progbits
 ; stel: .ent __fn_stub_sf_df
-; stel: la $25, sf_df
+; stel: lui $25, %hi(sf_df)
+; stel: addiu $25, $25, %lo(sf_df)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f13
 ; stel: jr $25
 ; stel: __fn_local_sf_df = sf_df
 ; stel: .end __fn_stub_sf_df
 
 ; Function Attrs: nounwind
 define float @sf_sf_sf(float %p1, float %p2) #0 {
 entry:
   %p1.addr = alloca float, align 4
   %p2.addr = alloca float, align 4
   store float %p1, float* %p1.addr, align 4
   store float %p2, float* %p2.addr, align 4
   %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
   %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
   %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
 ; stel: .section .mips16.fn.sf_sf_sf,"ax",@progbits
 ; stel: .ent __fn_stub_sf_sf_sf
-; stel: la $25, sf_sf_sf
+; stel: lui $25, %hi(sf_sf_sf)
+; stel: addiu $25, $25, %lo(sf_sf_sf)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f14
 ; stel: jr $25
 ; stel: __fn_local_sf_sf_sf = sf_sf_sf
 ; stel: .end __fn_stub_sf_sf_sf
 
 ; Function Attrs: nounwind
 define float @sf_sf_df(float %p1, double %p2) #0 {
 entry:
   %p1.addr = alloca float, align 4
   %p2.addr = alloca double, align 8
   store float %p1, float* %p1.addr, align 4
   store double %p2, double* %p2.addr, align 8
   %0 = load float, float* %p1.addr, align 4
   store float %0, float* @x, align 4
   %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
   %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
 ; stel: .section .mips16.fn.sf_sf_df,"ax",@progbits
 ; stel: .ent __fn_stub_sf_sf_df
-; stel: la $25, sf_sf_df
+; stel: lui $25, %hi(sf_sf_df)
+; stel: addiu $25, $25, %lo(sf_sf_df)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $6, $f14
 ; stel: mfc1 $7, $f15
 ; stel: jr $25
 ; stel: __fn_local_sf_sf_df = sf_sf_df
 ; stel: .end __fn_stub_sf_sf_df
 
 ; Function Attrs: nounwind
 define float @sf_df_sf(double %p1, float %p2) #0 {
 entry:
   %p1.addr = alloca double, align 8
   %p2.addr = alloca float, align 4
   store double %p1, double* %p1.addr, align 8
   store float %p2, float* %p2.addr, align 4
   %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
   %1 = load float, float* %p2.addr, align 4
   store float %1, float* @y, align 4
   %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
 ; stel: .section .mips16.fn.sf_df_sf,"ax",@progbits
 ; stel: .ent __fn_stub_sf_df_sf
-; stel: la $25, sf_df_sf
+; stel: lui $25, %hi(sf_df_sf)
+; stel: addiu $25, $25, %lo(sf_df_sf)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f13
 ; stel: mfc1 $6, $f14
 ; stel: jr $25
 ; stel: __fn_local_sf_df_sf = sf_df_sf
 ; stel: .end __fn_stub_sf_df_sf
 
 ; Function Attrs: nounwind
 define float @sf_df_df(double %p1, double %p2) #0 {
 entry:
   %p1.addr = alloca double, align 8
   %p2.addr = alloca double, align 8
   store double %p1, double* %p1.addr, align 8
   store double %p2, double* %p2.addr, align 8
   %0 = load double, double* %p1.addr, align 8
   store double %0, double* @xd, align 8
   %1 = load double, double* %p2.addr, align 8
   store double %1, double* @yd, align 8
   %2 = load float, float* @ret_sf, align 4
   ret float %2
 }
 
 ; stel: .section .mips16.fn.sf_df_df,"ax",@progbits
 ; stel: .ent __fn_stub_sf_df_df
-; stel: la $25, sf_df_df
+; stel: lui $25, %hi(sf_df_df)
+; stel: addiu $25, $25, %lo(sf_df_df)
 ; stel: mfc1 $4, $f12
 ; stel: mfc1 $5, $f13
 ; stel: mfc1 $6, $f14
 ; stel: mfc1 $7, $f15
 ; stel: jr $25
 ; stel: __fn_local_sf_df_df = sf_df_df
 ; stel: .end __fn_stub_sf_df_df
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Mips/hf1_body.ll

-; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picfp16
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \
+; RUN:     -relocation-model=pic -no-integrated-as < %s | \
+; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=GAS
+
+; The integrated assembler expands assembly macros before printing.
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \
+; RUN:     -relocation-model=pic < %s | \
+; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=IAS
 
 @x = external global float
 
 ; Function Attrs: nounwind
 define void @v_sf(float %p) #0 {
 entry:
   %p.addr = alloca float, align 4
   store float %p, float* %p.addr, align 4
   %0 = load float, float* %p.addr, align 4
   store float %0, float* @x, align 4
   ret void
 }
-; picfp16: .ent __fn_stub_v_sf
-; picfp16: .cpload $25
-; picfp16: .set reorder
-; picfp16: .reloc 0, R_MIPS_NONE, v_sf
-; picfp16: la $25, $__fn_local_v_sf
-; picfp16: mfc1 $4, $f12
-; picfp16: jr $25
-; picfp16: .end __fn_stub_v_sf
+; ALL-LABEL: .ent __fn_stub_v_sf
+; ALL:       .cpload $25
+; ALL:       .set reorder
+; ALL:       .reloc 0, R_MIPS_NONE, v_sf
+; GAS:       la $25, $__fn_local_v_sf
+; IAS:       lui $25, %hi(($$__fn_local_v_sf))
+; IAS:       addiu $25, $25, %lo(($$__fn_local_v_sf))
+; ALL:       mfc1 $4, $f12
+; ALL:       jr $25
+; ALL:       .end __fn_stub_v_sf

test/CodeGen/Mips/inlineasm-operand-code.ll

 ; Positive test for inline register constraints
 ;
 ; RUN: llc -no-integrated-as -march=mipsel < %s | \
 ; RUN:     FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s
 ; RUN: llc -no-integrated-as -march=mips < %s | \
 ; RUN:     FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s
 
+; IAS might not print in the same way since it parses the assembly.
+; RUN: llc -march=mipsel < %s | \
+; RUN:     FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=IAS %s
+; RUN: llc -march=mips < %s | \
+; RUN:     FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=IAS %s
+
 %union.u_tag = type { i64 }
 %struct.anon = type { i32, i32 }
 @uval = common global %union.u_tag zeroinitializer, align 8
 
 ; X with -3
 define i32 @constraint_X() nounwind {
 entry:
 ; ALL-LABEL: constraint_X:
 ; ALL:           #APP
 ; GAS:           addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
+; IAS:           addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
 ; ALL:           #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
   ret i32 0
 }
 
 ; x with -3
 define i32 @constraint_x() nounwind {
 entry:
 ; ALL-LABEL: constraint_x:
 ; ALL: #APP
 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
+; This is _also_ -3 because uimm16 values are silently coerced to simm16 when
+; it would otherwise fail to match.
+; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
 ; ALL: #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
   ret i32 0
 }
 
 ; d with -3
 define i32 @constraint_d() nounwind {
 entry:

 ; ALL:   #APP
 ; ALL:   addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
 ; ALL:   #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
   ret i32 0
 }
 
 ; z with -3
-define i32 @constraint_z() nounwind {
+define void @constraint_z_0() nounwind {
 entry:
-; ALL-LABEL: constraint_z:
+; ALL-LABEL: constraint_z_0:
 ; ALL:    #APP
 ; ALL:    addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
 ; ALL:    #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
+  ret void
+}
 
 ; z with 0
+define void @constraint_z_1() nounwind {
+entry:
+; ALL-LABEL: constraint_z_1:
 ; ALL:    #APP
-; GAS:    addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
+; GAS:    addu ${{[0-9]+}}, ${{[0-9]+}}, $0
+; IAS:    move ${{[0-9]+}}, ${{[0-9]+}}
 ; ALL:    #NO_APP
-  tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
+  tail call i32 asm sideeffect "addu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
+  ret void
+}
 
 ; z with non-zero and the "r"(register) and "J"(integer zero) constraints
+define void @constraint_z_2() nounwind {
+entry:
+; ALL-LABEL: constraint_z_2:
 ; ALL:    #APP
 ; ALL:    mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
 ; ALL:    #NO_APP
   call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
+  ret void
+}
 
 ; z with zero and the "r"(register) and "J"(integer zero) constraints
+define void @constraint_z_3() nounwind {
+entry:
+; ALL-LABEL: constraint_z_3:
 ; ALL:    #APP
-; ALL:    mtc0 $0, ${{[0-9]+}}
+; GAS:    mtc0 $0, ${{[0-9]+}}
+; IAS:    mtc0 $zero, ${{[0-9]+}}, 0
 ; ALL:    #NO_APP
   call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
+  ret void
+}
 
 ; z with non-zero and just the "r"(register) constraint
+define void @constraint_z_4() nounwind {
+entry:
+; ALL-LABEL: constraint_z_4:
 ; ALL:    #APP
 ; ALL:    mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
 ; ALL:    #NO_APP
   call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
+  ret void
+}
 
 ; z with zero and just the "r"(register) constraint
+define void @constraint_z_5() nounwind {
+entry:
+; ALL-LABEL: constraint_z_5:
 ; FIXME: Check for $0, instead of other registers.
 ;        We should be using $0 directly in this case, not real registers.
 ;        When the materialization of 0 gets fixed, this test will fail.
 ; ALL:    #APP
 ; ALL:    mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
 ; ALL:    #NO_APP
   call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
-  ret i32 0
+  ret void
 }
 
 ; A long long in 32 bit mode (use to assert)
 define i32 @constraint_longlong() nounwind {
 entry:
 ; ALL-LABEL: constraint_longlong:
 ; ALL:           #APP
 ; ALL:           addiu ${{[0-9]+}}, ${{[0-9]+}}, 3

test/CodeGen/Mips/inlineasm_constraint.ll

 ; RUN: llc -no-integrated-as -march=mipsel < %s | \
 ; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=GAS
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=ALL -check-prefix=IAS
 
 define void @constraint_I() nounwind {
 ; First I with short
 ; ALL-LABEL: constraint_I:
 ; ALL:           #APP
 ; ALL:           addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096
 ; ALL:           #NO_APP
   tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind
; ALL: #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
   ret void
 }
 
 define void @constraint_K() nounwind {
 ; Now K with 64
 ; ALL: #APP
 ; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
+; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 64
 ; ALL: #NO_APP  
   tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
   ret void
 }
 
 define void @constraint_L() nounwind {
 ; Now L with 0x00100000
 ; ALL: #APP