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Differential D18439

[mips] Range check simm32 and fold MIPS16's imm32 into simm32.
ClosedPublic

Authored by dsanders on Mar 24 2016, 4:45 AM.

Details

Reviewers
vkalintiris
Commits
rGb3c2764f8966: [mips] Range check simm32 and fold MIPS16's imm32 into simm32.
rL265302: [mips] Range check simm32 and fold MIPS16's imm32 into simm32.
Summary

At this point we should be able to enable IAS by default for O32 without
breaking check-all, or recursion.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 51535.Mar 24 2016, 4:45 AM
dsanders retitled this revision from to [mips] Range check simm32 and fold MIPS16's imm32 into simm32..
dsanders updated this object.
dsanders added a reviewer: vkalintiris.
dsanders added a subscriber: llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptMar 24 2016, 4:45 AM
vkalintiris accepted this revision.Mar 31 2016, 3:48 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Mar 31 2016, 3:48 AM
dsanders added a child revision: D18755: [mips] Trivial corrections to range checked immediates..Apr 4 2016, 8:04 AM
dsanders closed this revision.Apr 4 2016, 8:38 AM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
4 lines
6 lines
96 lines
test/
MC/
Mips/
18 lines

Diff 51535

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 3,809 Lines • ▼ Show 20 Lines case Match_SImm16_Relaxed:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 16-bit signed immediate"); "expected 16-bit signed immediate");
case Match_UImm20_0: case Match_UImm20_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 20-bit unsigned immediate"); "expected 20-bit unsigned immediate");
case Match_UImm26_0: case Match_UImm26_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 26-bit unsigned immediate"); "expected 26-bit unsigned immediate");
case Match_SImm32:
case Match_SImm32_Relaxed:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 32-bit signed immediate");
case Match_MemSImm9: case Match_MemSImm9:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected memory with 9-bit signed offset"); "expected memory with 9-bit signed offset");
case Match_MemGPSImm9: case Match_MemGPSImm9:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected memory with $gp and 9-bit signed offset"); "expected memory with $gp and 9-bit signed offset");
case Match_MemSImm10: case Match_MemSImm10:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
▲ Show 20 Lines • Show All 2,579 Lines • Show Last 20 Lines

lib/Target/Mips/Mips16InstrInfo.td

Show First 20 Lines • Show All 477 Lines • ▼ Show 20 Linesclass SelT<string op1, string op2>:
let isCodeGenOnly=1; let isCodeGenOnly=1;
let Constraints = "$rd = $rd_"; let Constraints = "$rd = $rd_";
let usesCustomInserter = 1; let usesCustomInserter = 1;
} }
// //
// 32 bit constant // 32 bit constant
// //
def imm32: Operand<i32>;
def Constant32: def Constant32:
MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; MipsPseudo16<(outs), (ins simm32:$imm), "\t.word $imm", []>;
def LwConstant32: def LwConstant32:
MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid), MipsPseudo16<(outs CPU16Regs:$rx), (ins simm32:$imm, simm32:$constid),
"lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
// //
// Some general instruction class info // Some general instruction class info
// //
// //
▲ Show 20 Lines • Show All 1,417 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 456 Lines • ▼ Show 20 Lines
// The term 'superset' starts to break down here since the uimm5_plus* classes // The term 'superset' starts to break down here since the uimm5_plus* classes
// are not true supersets of uimm5 (but they are still subsets of uimm6). // are not true supersets of uimm5 (but they are still subsets of uimm6).
// * 'Relaxed' immediates are supersets of the corresponding unsigned immediate. // * 'Relaxed' immediates are supersets of the corresponding unsigned immediate.
// uimm16 < uimm16_relaxed // uimm16 < uimm16_relaxed
// * The codeGen pattern type is arbitrarily ordered. // * The codeGen pattern type is arbitrarily ordered.
// uimm5 < uimm5_64, and uimm5 < vsplat_uimm5 // uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
// This is entirely arbitrary. We need an ordering and what we pick is // This is entirely arbitrary. We need an ordering and what we pick is
// unimportant since only one is possible for a given mnemonic. // unimportant since only one is possible for a given mnemonic.
def SImm32RelaxedAsmOperandClass
: SImmAsmOperandClass<32, []> {
let Name = "SImm32_Relaxed";
let PredicateMethod = "isAnyImm<32>";
let DiagnosticType = "SImm32_Relaxed";
}
def SImm32AsmOperandClass
: SImmAsmOperandClass<32, [SImm32RelaxedAsmOperandClass]>;
def ConstantUImm26AsmOperandClass def ConstantUImm26AsmOperandClass
: ConstantUImmAsmOperandClass<26, []>; : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>;
def ConstantUImm20AsmOperandClass def ConstantUImm20AsmOperandClass
: ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>; : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
def UImm16RelaxedAsmOperandClass def UImm16RelaxedAsmOperandClass
: UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> { : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
let Name = "UImm16_Relaxed"; let Name = "UImm16_Relaxed";
let PredicateMethod = "isAnyImm<16>"; let PredicateMethod = "isAnyImm<16>";
let DiagnosticType = "UImm16_Relaxed"; let DiagnosticType = "UImm16_Relaxed";
} }
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} }
def simm18_lsl3 : Operand<i32> { def simm18_lsl3 : Operand<i32> {
let EncoderMethod = "getSimm18Lsl3Encoding"; let EncoderMethod = "getSimm18Lsl3Encoding";
let DecoderMethod = "DecodeSimm18Lsl3"; let DecoderMethod = "DecodeSimm18Lsl3";
let ParserMatchClass = MipsJumpTargetAsmOperand; let ParserMatchClass = MipsJumpTargetAsmOperand;
} }
def simm32 : Operand<i32>;
// Zero // Zero
def uimmz : Operand<i32> { def uimmz : Operand<i32> {
let PrintMethod = "printUImm<0>"; let PrintMethod = "printUImm<0>";
let ParserMatchClass = ConstantImmzAsmOperandClass; let ParserMatchClass = ConstantImmzAsmOperandClass;
} }
// size operand of ins instruction // size operand of ins instruction
def uimm_range_2_64 : Operand<i32> { def uimm_range_2_64 : Operand<i32> {
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Linesforeach I = {5, 10} in
} }
def simm7_lsl2 : Operand<OtherVT> { def simm7_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getSImm7Lsl2Encoding"; let EncoderMethod = "getSImm7Lsl2Encoding";
let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>"; let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ", 0, 4>";
let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass; let ParserMatchClass = ConstantSImm7Lsl2AsmOperandClass;
} }
def simm16 : Operand<i32> { foreach I = {16, 32} in
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; def simm # I : Operand<i32> {
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass"); let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
let ParserMatchClass = !cast<AsmOperandClass>("SImm" # I # "AsmOperandClass");
} }
// Like simm16 but coerces uimm16 to simm16. // Like simm16 but coerces uimm16 to simm16.
def simm16_relaxed : Operand<i32> { def simm16_relaxed : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
let ParserMatchClass = !cast<AsmOperandClass>("SImm16RelaxedAsmOperandClass"); let ParserMatchClass = !cast<AsmOperandClass>("SImm16RelaxedAsmOperandClass");
} }
def simm16_64 : Operand<i64> { def simm16_64 : Operand<i64> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>"; let DecoderMethod = "DecodeSImmWithOffsetAndScale<16>";
let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass"); let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
} }
// Like simm32 but coerces uimm32 to simm32.
def simm32_relaxed : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";
let ParserMatchClass = !cast<AsmOperandClass>("SImm32RelaxedAsmOperandClass");
}
// This is almost the same as a uimm7 but 0x7f is interpreted as -1. // This is almost the same as a uimm7 but 0x7f is interpreted as -1.
def li16_imm : Operand<i32> { def li16_imm : Operand<i32> {
let DecoderMethod = "DecodeLi16Imm"; let DecoderMethod = "DecodeLi16Imm";
let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass; let ParserMatchClass = ConstantUImm7Sub1AsmOperandClass;
} }
def pcrel16 : Operand<i32> { def pcrel16 : Operand<i32> {
▲ Show 20 Lines • Show All 1,298 Lines • ▼ Show 20 Lines
} }
def : MipsInstAlias<"move $dst, $src", def : MipsInstAlias<"move $dst, $src",
(ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>, (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
GPR_32 { GPR_32 {
let AdditionalPredicates = [NotInMicroMips]; let AdditionalPredicates = [NotInMicroMips];
} }
def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"addu $rs, $rt, $imm", def : MipsInstAlias<
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; "addu $rs, $rt, $imm",
def : MipsInstAlias<"addu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>; def : MipsInstAlias<
def : MipsInstAlias<"add $rs, $rt, $imm", "addu $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>, (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"add $rs, $rt, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"add $rs, $imm", def : MipsInstAlias<
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>, "add $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"and $rs, $rt, $imm", def : MipsInstAlias<
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; "and $rs, $rt, $imm",
def : MipsInstAlias<"and $rs, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>; def : MipsInstAlias<
"and $rs, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
let Predicates = [NotInMicroMips] in { let Predicates = [NotInMicroMips] in {
def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
} }
def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
def : MipsInstAlias<"not $rt, $rs", def : MipsInstAlias<"not $rt, $rs",
(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
def : MipsInstAlias<"neg $rt, $rs", def : MipsInstAlias<"neg $rt, $rs",
(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"negu $rt", def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"negu $rt, $rs", def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
def : MipsInstAlias<"slt $rs, $rt, $imm", def : MipsInstAlias<
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; "slt $rs, $rt, $imm",
def : MipsInstAlias<"sltu $rt, $rs, $imm", (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32:$imm), 0>; def : MipsInstAlias<
def : MipsInstAlias<"xor $rs, $rt, $imm", "sltu $rt, $rs, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<"xor $rs, $imm", def : MipsInstAlias<
(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>; "xor $rs, $rt, $imm",
def : MipsInstAlias<"or $rs, $rt, $imm", (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), 0>; def : MipsInstAlias<
def : MipsInstAlias<"or $rs, $imm", "xor $rs, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32:$imm), 0>; (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"or $rs, $rt, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
def : MipsInstAlias<
"or $rs, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
} }
def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>; def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>; def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>; def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesdef : MipsInstAlias<"srl $rd, $rt, $rs",
(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsInstAlias<"sync", def : MipsInstAlias<"sync",
(SYNC 0), 1>, ISA_MIPS2; (SYNC 0), 1>, ISA_MIPS2;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Assembler Pseudo Instructions // Assembler Pseudo Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// We use i32imm on li/la to defer range checking to the assembler.
class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> : class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
!strconcat(instr_asm, "\t$rt, $imm32")> ; !strconcat(instr_asm, "\t$rt, $imm32")> ;
def LoadImm32 : LoadImmediate32<"li", simm32, GPR32Opnd>; def LoadImm32 : LoadImmediate32<"li", i32imm, GPR32Opnd>;
class LoadAddressFromReg32<string instr_asm, Operand MemOpnd, class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
RegisterOperand RO> : RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
!strconcat(instr_asm, "\t$rt, $addr")> ; !strconcat(instr_asm, "\t$rt, $addr")> ;
def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>; def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> : class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
!strconcat(instr_asm, "\t$rt, $imm32")> ; !strconcat(instr_asm, "\t$rt, $imm32")> ;
def LoadAddrImm32 : LoadAddressFromImm32<"la", simm32, GPR32Opnd>; def LoadAddrImm32 : LoadAddressFromImm32<"la", i32imm, GPR32Opnd>;
def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
"jal\t$rd, $rs"> ; "jal\t$rd, $rs"> ;
def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs), def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
"jal\t$rs"> ; "jal\t$rs"> ;
def NORImm : MipsAsmPseudoInst< def NORImm : MipsAsmPseudoInst<
(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm), (outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm),
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test/MC/Mips/instalias-imm-expanding.s

Show All 16 Lines
# CHECK: addi $4, $4, 0 # encoding: [0x00,0x00,0x84,0x20] # CHECK: addi $4, $4, 0 # encoding: [0x00,0x00,0x84,0x20]
add $4, 0xFFFF add $4, 0xFFFF
# CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34] # CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34]
# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00] # CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
add $4, 0x10000 add $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00] # CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
add $4, 0xFFFFFFFF add $4, 0xFFFFFFFF
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: addi $4, $4, -1 # encoding: [0xff,0xff,0x84,0x20]
# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
add $4, $5, -0x80000000 add $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, -0x8001 add $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, -0x8000 add $4, $5, -0x8000
# CHECK: addi $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x20] # CHECK: addi $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x20]
add $4, $5, 0 add $4, $5, 0
# CHECK: addi $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x20] # CHECK: addi $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x20]
add $4, $5, 0xFFFF add $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, 0x10000 add $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00] # CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
add $4, $5, 0xFFFFFFFF add $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: addi $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x20]
# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
addu $4, -0x80000000 addu $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, -0x8001 addu $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, -0x8000 addu $4, -0x8000
# CHECK: addiu $4, $4, -32768 # encoding: [0x00,0x80,0x84,0x24] # CHECK: addiu $4, $4, -32768 # encoding: [0x00,0x80,0x84,0x24]
addu $4, 0 addu $4, 0
# CHECK: addiu $4, $4, 0 # encoding: [0x00,0x00,0x84,0x24] # CHECK: addiu $4, $4, 0 # encoding: [0x00,0x00,0x84,0x24]
addu $4, 0xFFFF addu $4, 0xFFFF
# CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34] # CHECK: ori $1, $zero, 65535 # encoding: [0xff,0xff,0x01,0x34]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, 0x10000 addu $4, 0x10000
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00] # CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, 0xFFFFFFFF addu $4, 0xFFFFFFFF
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK: addiu $4, $4, -1 # encoding: [0xff,0xff,0x84,0x24]
# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
addu $4, $5, -0x80000000 addu $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, -0x8001 addu $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, -0x8000 addu $4, $5, -0x8000
# CHECK: addiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x24] # CHECK: addiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x24]
addu $4, $5, 0 addu $4, $5, 0
# CHECK: addiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x24] # CHECK: addiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x24]
addu $4, $5, 0xFFFF addu $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, 0x10000 addu $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00] # CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
addu $4, $5, 0xFFFFFFFF addu $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: addiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x24]
# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
and $4, -0x80000000 and $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
and $4, -0x8001 and $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00] # CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines# CHECK: slti $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x28]
slt $4, $5, 0 slt $4, $5, 0
# CHECK: slti $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x28] # CHECK: slti $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x28]
slt $4, $5, 0xFFFF slt $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
slt $4, $5, 0x10000 slt $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00] # CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
slt $4, $5, 0xFFFFFFFF slt $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28]
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
sltu $4, $5, -0x80000000 sltu $4, $5, -0x80000000
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c] # CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
sltu $4, $5, -0x8001 sltu $4, $5, -0x8001
# CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c] # CHECK: lui $4, 65535 # encoding: [0xff,0xff,0x04,0x3c]
# CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34] # CHECK: ori $4, $4, 32767 # encoding: [0xff,0x7f,0x84,0x34]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
sltu $4, $5, -0x8000 sltu $4, $5, -0x8000
# CHECK: sltiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x2c] # CHECK: sltiu $4, $5, -32768 # encoding: [0x00,0x80,0xa4,0x2c]
sltu $4, $5, 0 sltu $4, $5, 0
# CHECK: sltiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x2c] # CHECK: sltiu $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x2c]
sltu $4, $5, 0xFFFF sltu $4, $5, 0xFFFF
# CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34] # CHECK: ori $4, $zero, 65535 # encoding: [0xff,0xff,0x04,0x34]
sltu $4, $5, 0x10000 sltu $4, $5, 0x10000
# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c] # CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00] # CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
sltu $4, $5, 0xFFFFFFFF sltu $4, $5, 0xFFFFFFFF
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24] # CHECK: sltiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x2c]
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
xor $4, -0x80000000 xor $4, -0x80000000
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] # CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
xor $4, -0x8001 xor $4, -0x8001
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c] # CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34] # CHECK: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00] # CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
Show All 33 Lines