AMDGPU/SI: Do not generate s_waitcnt for ds_permute/ds_bpermute Instructions.

[cfang]

Summary

ds_permute/ds_bpermute Instructions do not actually read memory.

[• tstellarAMD]

LGTM, but can you add a testcase for this.

[cfang]

Add test case for ds_permute/ds_bpermute NOT generating s_waitcnts

[• tstellarAMD]

LGTM. Just a few suggestions to improve the tests before you commit it.

test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll

15 ↗

(On Diff #50888)

You might want to add a CHECK here for the branch instruction. This will make it more robust.

test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll

15 ↗

(On Diff #50888)

Same here.

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 }
 
 multiclass DS_1A1D_PERMUTE <bits<8> op, string opName, RegisterClass rc,
                             SDPatternOperator node = null_frag,
   dag outs = (outs rc:$vdst),
   dag ins = (ins VGPR_32:$addr, rc:$data0),
   string asm = opName#" $vdst, $addr, $data0"> {
 
-  let mayLoad = 0, mayStore = 0, isConvergent = 1 in {
+  let LGKM_CNT = 0, mayLoad = 0, mayStore = 0, isConvergent = 1 in {
     def "" : DS_Pseudo <opName, outs, ins,
      [(set (i32 rc:$vdst),
          (node (i32 VGPR_32:$addr), (i32 rc:$data0)))]>;
 
     let data1 = 0, offset0 = 0, offset1 = 0, gds = 0  in {
       def "_vi" : DS_Real_vi <op, opName, outs, ins, asm>;
     }
   }

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll

 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
 
 declare i32 @llvm.amdgcn.ds.bpermute(i32, i32) #0
 
 ; FUNC-LABEL: {{^}}ds_bpermute:
 ; CHECK: ds_bpermute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 define void @ds_bpermute(i32 addrspace(1)* %out, i32 %index, i32 %src) nounwind {
   %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %index, i32 %src) #0
   store i32 %bpermute, i32 addrspace(1)* %out, align 4
   ret void
 }
 
+; FUNC-LABEL: {{^}}bpermute_no_waitcnt_test:
+; CHECK: s_cbranch_scc1
+; CHECK: ds_bpermute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; CHECK-NOT: s_waitcnt
+define void @bpermute_no_waitcnt_test(i32 addrspace(1)* %out, i32 %cond) {
+entry:
+
+  %tmp = icmp eq i32 %cond, 0
+  br i1 %tmp, label %if, label %else
+
+if:                                               ; preds = %entry
+
+  %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 0, i32 0) #0
+  br label %endif
+
+else:                                             ; preds = %entry
+  br label %endif
+
+endif:
+  %val = phi i32 [ %bpermute, %if ], [0, %else]      ; preds = %else, %if
+  store i32 %val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
 attributes #0 = { nounwind readnone convergent }

llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll

 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
 
 declare i32 @llvm.amdgcn.ds.permute(i32, i32) #0
 
 ; FUNC-LABEL: {{^}}ds_permute:
 ; CHECK: ds_permute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 define void @ds_permute(i32 addrspace(1)* %out, i32 %index, i32 %src) nounwind {
-  %bpermute = call i32 @llvm.amdgcn.ds.permute(i32 %index, i32 %src) #0
-  store i32 %bpermute, i32 addrspace(1)* %out, align 4
+  %permute = call i32 @llvm.amdgcn.ds.permute(i32 %index, i32 %src) #0
+  store i32 %permute, i32 addrspace(1)* %out, align 4
   ret void
 }
 
+; FUNC-LABEL: {{^}}permute_no_waitcnt_test:
+; CHECK: s_cbranch_scc1
+; CHECK: ds_permute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; CHECK-NOT: s_waitcnt
+define void @permute_no_waitcnt_test(i32 addrspace(1)* %out, i32 %cond) {
+entry:
+
+  %tmp = icmp eq i32 %cond, 0
+  br i1 %tmp, label %if, label %else
+
+if:                                               ; preds = %entry
+  %permute = call i32 @llvm.amdgcn.ds.permute(i32 0, i32 0) #0
+  br label %endif
+
+else:                                             ; preds = %entry
+  br label %endif
+
+endif:
+  %val = phi i32 [ %permute, %if ], [0, %else]      ; preds = %else, %if
+  store i32 %val, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+
 attributes #0 = { nounwind readnone convergent }