Add support for preserve_most/preserve_all calling conventions to the AArch64 backend.

[swiftix]

Summary

This change add a support for preserve_most/preserve_all calling conventions to the AArch64 backend, similar to how it was done for X86-64.

There is also a subsequent patch on top of this one to add a tail-calls support for these calling conventions.

[t.p.northover]

lib/Target/AArch64/AArch64CallingConvention.td

314–315

I think some more comments on the choices here would be useful. Obviously you can't preserve x16 or x17 because the linker may use them to resolve a PLT call, and x18 is the platform register on Darwin.

But you're excluding x15 too, which makes "RT_AllRegs" increasingly misnamed (it also excludes the high half of vector registers and the argument registers).

[swiftix]

lib/Target/AArch64/AArch64CallingConvention.td

314–315

x15 was excluded, because AArch64 backend seems to need pairs of registers, when it store/restores them in the epilogue. With x15 included, we get an odd number of registers to store/restore, which triggers an assertion in the backend.

The argument registers were not included (yet), because LLVM seems to have problems in situations, where a set of callee-saved registers overlaps with the sets of argument/return registers. In particular, it led the incorrect code being produced, when functions using these new calling conventions call each other or are using tail calls. I've filed a couple of radars about it, but they are not resolved yet.

314–315

As for RT_AllRegs, you are probably right. Currently we do not really use this convention on AArch64, it was implemented more for a sake of completeness.

But may be indeed, we should add x15 and the high half of vector registers and the argument registers there.

[swiftix]

lib/Target/AArch64/AArch64CallingConvention.td

314–315

x15 was excluded, because AArch64 backend seems to need pairs of registers, when it store/restores them in the epilogue. With x15 included, we get an odd number of registers to store/restore, which triggers an assertion in the backend.

The argument registers were not included (yet), because LLVM seems to have problems in situations, where a set of callee-saved registers overlaps with the sets of argument/return registers. In particular, it led the incorrect code being produced, when functions using these new calling conventions call each other or are using tail calls. I've filed a couple of radars about it, but they are not resolved yet.

[swiftix]

I addressed the comments in http://reviews.llvm.org/D18016.

• PreserveMost callee-saves X15 now, because the backend can support it in the meantime.
• After a discussion with Tim, I decided to remove preserve_all support for the time being, as it is not really used yet and the set of registers it should callee-save is not quite settled yet.

lib/Target/AArch64/AArch64CallingConvention.td

 def CSR_AArch64_AllRegs
     : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
                            (sequence "X%u", 0, 28), FP, LR, SP,
                            (sequence "B%u", 0, 31), (sequence "H%u", 0, 31),
                            (sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
                            (sequence "Q%u", 0, 31))>;
 
 def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>;
+
+def CSR_AArch64_RT_MostRegs :  CalleeSavedRegs<(add CSR_AArch64_AAPCS,
+                                                (sequence "X%u", 9, 14))>;
+
+// Same as CSR_AArch64_RT_MostRegs, but saves all 64-bit SIMD/FP registers.
+def CSR_AArch64_RT_AllRegs :  CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs,
+                                                (sequence "D%u", 0, 31))>;
+

lib/Target/AArch64/AArch64ISelLowering.cpp

CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
   default:
     llvm_unreachable("Unsupported calling convention.");
   case CallingConv::WebKit_JS:
     return CC_AArch64_WebKit_JS;
   case CallingConv::GHC:
     return CC_AArch64_GHC;
   case CallingConv::C:
   case CallingConv::Fast:
+  case CallingConv::PreserveMost:
+  case CallingConv::PreserveAll:
     if (!Subtarget->isTargetDarwin())
       return CC_AArch64_AAPCS;
     return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
   }
 }
 
 SDValue AArch64TargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,

lib/Target/AArch64/AArch64RegisterInfo.cpp

if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
     // used for passing STG regs around
     return CSR_AArch64_NoRegs_SaveList;
   if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
     return CSR_AArch64_AllRegs_SaveList;
   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)
     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
            CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
            CSR_AArch64_CXX_TLS_Darwin_SaveList;
+  if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost)
+    return CSR_AArch64_RT_MostRegs_SaveList;
+  if (MF->getFunction()->getCallingConv() == CallingConv::PreserveAll)
+    return CSR_AArch64_RT_AllRegs_SaveList;
   else
     return CSR_AArch64_AAPCS_SaveList;
 }
 
 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
     const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
     return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
   return nullptr;
 }
 
 const uint32_t *
 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                           CallingConv::ID CC) const {
   if (CC == CallingConv::GHC)
     // This is academic becase all GHC calls are (supposed to be) tail calls
     return CSR_AArch64_NoRegs_RegMask;
   if (CC == CallingConv::AnyReg)
     return CSR_AArch64_AllRegs_RegMask;
   if (CC == CallingConv::CXX_FAST_TLS)
     return CSR_AArch64_CXX_TLS_Darwin_RegMask;
+  if (CC == CallingConv::PreserveMost)
+    return CSR_AArch64_RT_MostRegs_RegMask;
+  if (CC == CallingConv::PreserveAll)
+    return CSR_AArch64_RT_AllRegs_RegMask;
   else
     return CSR_AArch64_AAPCS_RegMask;
 }
 
 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const {
   if (TT.isOSDarwin())
     return CSR_AArch64_TLS_Darwin_RegMask;
 

lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
                                            bool isVarArg) const {
   switch (CC) {
   default:
     llvm_unreachable("Unsupported calling convention");
   case CallingConv::ARM_AAPCS:
   case CallingConv::ARM_APCS:
   case CallingConv::GHC:
     return CC;
+  case CallingConv::PreserveMost:
+    return CallingConv::PreserveMost;
+  case CallingConv::PreserveAll:
+    return CallingConv::PreserveAll;
   case CallingConv::ARM_AAPCS_VFP:
     return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
   case CallingConv::C:
     if (!Subtarget->isAAPCS_ABI())
       return CallingConv::ARM_APCS;
     else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
              getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
              !isVarArg)
CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
   case CallingConv::ARM_AAPCS:
     return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
   case CallingConv::ARM_AAPCS_VFP:
     return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
   case CallingConv::Fast:
     return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
   case CallingConv::GHC:
     return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
+  case CallingConv::PreserveMost:
+    return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
+  case CallingConv::PreserveAll:
+    return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
   }
 }
 
 /// LowerCallResult - Lower the result values of a call into the
 /// appropriate copies out of appropriate physical registers.
 SDValue
 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
                                    CallingConv::ID CallConv, bool isVarArg,

test/CodeGen/AArch64/preserve_allcc.ll

+; RUN: llc < %s -mtriple=arm64-apple-ios-8.0.0 | FileCheck %s
+
+declare void @standard_cc_func()
+declare preserve_mostcc void @preserve_mostcc_func()
+declare preserve_allcc void @preserve_allcc_func()
+
+; Registers r9-r14, d0-d7, d16-d31 should be saved before the call of a function
+; with a standard calling convention.
+define preserve_allcc void @preserve_allcc1() nounwind {
+entry:
+;CHECK-LABEL: preserve_allcc1
+;CHECK-NOT:   stp
+;CHECK:       stp d31, d30,
+;CHECK:       stp d29, d28,
+;CHECK:       stp d27, d26,
+;CHECK:       stp d25, d24,
+;CHECK:       stp d23, d22,
+;CHECK:       stp d21, d20,
+;CHECK:       stp d19, d18,
+;CHECK:       stp d17, d16,
+;CHECK:       stp d7, d6,
+;CHECK:       stp d5, d4,
+;CHECK:       stp d3, d2,
+;CHECK:       stp d1, d0,
+;CHECK:       stp x14, x13,
+;CHECK:       stp x12, x11,
+;CHECK:       stp x10, x9,
+;CHECK:       stp x29, x30,
+;CHECK:       bl      _standard_cc_func
+  call void @standard_cc_func()
+;CHECK:       ldp x29, x30,
+;CHECK:       ldp x10, x9,
+;CHECK:       ldp x12, x11,
+;CHECK:       ldp x14, x13,
+;CHECK:       ldp d1, d0,
+;CHECK:       ldp d3, d2,
+;CHECK:       ldp d5, d4,
+;CHECK:       ldp d7, d6,
+;CHECK:       ldp d17, d16,
+;CHECK:       ldp d19, d18,
+;CHECK:       ldp d21, d20,
+;CHECK:       ldp d23, d22,
+;CHECK:       ldp d25, d24,
+;CHECK:       ldp d27, d26,
+;CHECK:       ldp d29, d28,
+;CHECK:       ldp d31, d30,
+  ret void
+}
+
+; Registers r9-r14 and d0-d7, d16-d31 don't need to be saved if one
+; function with preserve_allcc calling convention calls another
+; function with preserve_allcc calling convention, because the
+; callee wil save these registers anyways.
+define preserve_allcc void @preserve_allcc2() nounwind {
+entry:
+;CHECK-LABEL: preserve_allcc2
+;CHECK-NOT: x14
+;CHECK:     stp     x29, x30, [sp, #-16]!
+;CHECK-NOT: x14
+;CHECK:     bl      _preserve_allcc_func
+  call preserve_allcc void @preserve_allcc_func()
+  ret void
+}
+
+; Registers d0-d7 and d16-d31 should be saved before the call of a function
+; with a preserve_mostcc calling convention.
+define preserve_allcc void @preserve_allcc3() nounwind {
+entry:
+;CHECK-LABEL: preserve_allcc3
+;CHECK-NOT:   stp
+;CHECK:       stp d31, d30,
+;CHECK:       stp d29, d28,
+;CHECK:       stp d27, d26,
+;CHECK:       stp d25, d24,
+;CHECK:       stp d23, d22,
+;CHECK:       stp d21, d20,
+;CHECK:       stp d19, d18,
+;CHECK:       stp d17, d16,
+;CHECK:       stp d7, d6,
+;CHECK:       stp d5, d4,
+;CHECK:       stp d3, d2,
+;CHECK:       stp d1, d0,
+;CHECK:       stp x29, x30,
+;CHECK:       bl      _preserve_mostcc_func
+  call preserve_mostcc void @preserve_mostcc_func()
+;CHECK:       ldp x29, x30,
+;CHECK:       ldp d1, d0,
+;CHECK:       ldp d3, d2,
+;CHECK:       ldp d5, d4,
+;CHECK:       ldp d7, d6,
+;CHECK:       ldp d17, d16,
+;CHECK:       ldp d19, d18,
+;CHECK:       ldp d21, d20,
+;CHECK:       ldp d23, d22,
+;CHECK:       ldp d25, d24,
+;CHECK:       ldp d27, d26,
+;CHECK:       ldp d29, d28,
+;CHECK:       ldp d31, d30,
+  ret void
+}
+

test/CodeGen/AArch64/preserve_mostcc.ll

+; RUN: llc < %s -mtriple=arm64-apple-ios-8.0.0 | FileCheck %s
+
+declare void @standard_cc_func()
+declare preserve_mostcc void @preserve_mostcc_func()
+
+; Registers r9-r14 should be saved before the call of a function
+; with a standard calling convention.
+define preserve_mostcc void @preserve_mostcc1() nounwind {
+entry:
+;CHECK-LABEL: preserve_mostcc1
+;CHECK-NOT:   stp
+;CHECK:       stp     x14, x13,
+;CHECK-NEXT:  stp     x12, x11,
+;CHECK-NEXT:  stp     x10, x9,
+;CHECK:       bl      _standard_cc_func
+  call void @standard_cc_func()
+;CHECK:       ldp     x10, x9,
+;CHECK-NEXT:  ldp     x12, x11,
+;CHECK-NEXT:  ldp     x14, x13,
+  ret void
+}
+
+; Registers r9-r14 don't need to be saved if one
+; function with preserve_mostcc calling convention calls another
+; function with preserve_mostcc calling convention, because the
+; callee wil save these registers anyways.
+define preserve_mostcc void @preserve_mostcc2() nounwind {
+entry:
+;CHECK-LABEL: preserve_mostcc2
+;CHECK-NOT: x14
+;CHECK:     stp     x29, x30,
+;CHECK-NOT: x14
+;CHECK:     bl      _preserve_mostcc_func
+  call preserve_mostcc void @preserve_mostcc_func()
+  ret void
+}
+