Fix for PR 26617 (disable scalar-to-vector conversions using direct moves for 32-bit targets)

[nemanjai]

Summary

When I implemented these conversions, I didn't consider what the results would be if someone attempted to build 32-bit applications on targets that have direct moves. This just disables the problematic conversions when 32-bit registers are used.

[nemanjai]

Added the test case that I forgot to svn add.

[kbarton]

lib/Target/PowerPC/PPCISelLowering.cpp

560

The definition of use64BitRegs is confusing to me.
Could you use Subtarget.isPPC64() instead? We basically only want to do this when we are in 64-bit mode, as I understand it.

[nemanjai]

lib/Target/PowerPC/PPCISelLowering.cpp

560

I only used this because it most closely encapsulates the conditions under which we aren't able to perform these actions. However, I think the simplest thing would indeed be to use Subtarget.isPPC64() (or even the local isPPC64) instead. I'll change it and test it prior to committing.

I'll change it to:

if (Subtarget.hasDirectMove() && isPPC64)

[kbarton]

LGTM

[nemanjai]

Committed revision 264282.

lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasAltivec()) {
 
     if (Subtarget.hasVSX()) {
       setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
       if (Subtarget.hasP8Vector()) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
       }
-      if (Subtarget.hasDirectMove()) {
+      if (Subtarget.hasDirectMove() && Subtarget.use64BitRegs()) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);

test/CodeGen/PowerPC/pr26617.ll

+; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
+define i32 @test(<4 x i32> %v, i32 %elem) #0 {
+entry:
+  %vecext = extractelement <4 x i32> %v, i32 %elem
+  ret i32 %vecext
+}
+; CHECK: stxvw4x 34,
+; CHECK: lwzx 3,