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X86: Load and ZeroExtend i1 value
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Authored by delena on Feb 23 2016, 4:15 AM.

Details

Summary

Optimized loading (zextload) of i1 value from memory.
This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793.
Extra "and" causes performance degradation.

We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits.
I described this assumption in the documentation.

Diff Detail

Repository
rL LLVM

Event Timeline

delena updated this revision to Diff 48804.Feb 23 2016, 4:15 AM
delena retitled this revision from to X86: Load and ZeroExtend i1 value.
delena updated this object.
delena set the repository for this revision to rL LLVM.
delena added subscribers: llvm-commits, igorb.
qcolombet added inline comments.Feb 23 2016, 9:38 AM
../docs/LangRef.rst
1756 ↗(On Diff #48804)

I don’t think this part of the patch makes sense.
This may be the right thing to do for x86 but maybe not for all the targets. Ih other words, I don’t think we want to make this a requirement for all targets, unless this was already a requirement we forgot to document so far?

../lib/Target/X86/X86InstrCompiler.td
1142–1146

Add the comment regarding i1 being zero extended before store here.

delena updated this revision to Diff 48887.Feb 23 2016, 11:13 PM

I moved the comment regarding i1 memory form from the common LangRef to X86InstrCompiler.td file.

qcolombet accepted this revision.Feb 24 2016, 9:58 AM
qcolombet edited edge metadata.

Hi Elena,

LGTM.

Thanks,
-Quentin

This revision is now accepted and ready to land.Feb 24 2016, 9:58 AM
DavidKreitzer edited edge metadata.Feb 24 2016, 1:56 PM

Thanks for doing this, Elena. LGTM also.

This revision was automatically updated to reflect the committed changes.