[LLDB][MIPS] Single step atomic sequences

[bhushan]

Summary

This patch handles atomic sequences during single step.

LLDB should treat all instructions in the atomic sequence as if they are a single instruction i.e as a "single instruction block".
So while single stepping, LLDB should detect and skip such sequence by placing breakpoints only outside of such sequence i.e at the end of the sequence.

In MIPS, atomic sequence starts with LL (linked load) instruction and end with SC (store conditional) instruction.

Example of atomic sequence in MIPS:

0x400c08 <+372>: ll     $4, 0($2) ----> Start of sequence
0x400c0c <+376>: bne    $4, $5, 28    ---> Atomic sequence can contain branches that jump outside sequence range.
0x400c10 <+380>: addiu  $3, $zero, 0
0x400c14 <+384>: move   $1, $6
0x400c18 <+388>: sc     $1, 0($2) -----> End of sequence
0x400c1c <+392>: beqz   $1, -20   
0x400c20 <+396>: addiu  $3, $zero, 1
0x400c24 <+400>: sync
0x400c28 <+404>: bnez   $3, 16    ---> Target of branch from sequence

Considering above example, while single stepping from LL instruction, LLDB should stop at instruction
after the end of sequence (instead of stopping at instruction next to LL).

There can be multiple exit/end points to atomic sequence.

1. SC instruction
2. Branch instructions in atomic sequence that jump outside sequence.

So to handle this, LLDB should place breakpoints at multiple locations:

1. Breakpoint at instruction after SC instruction (i.e at 0x400c1c in above ex)
2. Breakpoints at target addresses of branch instructions (if the branch target address is outside the sequence) i.e at 0x400c28, target of "bne $4, $5, 28" instruction.

These breakpoint addresses are determined by EmulateInstruction.

This patch makes few assumptions:

1. Assumes that no atomic sequence for mips is longer than 16 instructions. i.e scan upto maximum 16 instructions from LL to find end of sequence.
2. Assumes that the atomic sequence ends with a sc/scd instruction. So if we dont find "sc/scd" instruction then do not put any breakpoint. i.e fallback to the standard single-step code.

Testcase:

This patch also adds a testcase "TestStepInAtomicSequence.py" to test this change (currently enabled for MIPS only).
The test finds starting instruction of atomic sequence, runs till that instruction then does a single step and
finally verifies that we have stopped after end of sequence.

[labath]

I'll leave the final review to Tamas, just a couple of comments here.

packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/TestStepInAtomicSequence.py

70

If you don't find the instructions you are looking for (perhaps due to a compiler change), the test will end up being a no-op. You might want to assert that you actually find the instructions you are looking for.

94

These kinds of debug statements are usually made conditional on self.TraceOn() (-t flag to dotest), to minimize the noise it the general case when you're not debugging this test.

source/Plugins/Process/Linux/NativeProcessLinux.cpp

1689

I've been seeing this pattern a lot lately. Isn't it time to make a isMipsArchitecture utility function somewhere?

[clayborg]

Looks good to me, but I think Jim Ingham should have a look in case he has anything to add since Jim is the master or stepping.

[tberghammer]

I am not sure I agree with the following starting point of the CL (I know about the similar functionality in GDB) and even if we agree in it I think you are handling a very small fraction of the problems.

LLDB should treat all instructions in the atomic sequence as if they are a single instruction i.e as a "single instruction block".

I think there are 3 scenario around atomic sequences:

1. You are setting a breakpoint what fails inside of the atomic sequence
2. You are line level stepping over an atomic sequence
3. You are instruction level single stepping over an atomic sequence

For me the expected behavior in scenario 1 and 2 is to set the breakpoint at the address specified and handle the atomic sequence when you try to continue from the breakpoint (I hope that the compilers are generally not putting line breaks / symbols in the middle of an atomic sequence). I think the 3. scenario will happen when you are doing assembly level debugging of an atomic sequence where I would expect to step only 1 instruction as I am debugging assembly code.

If I understand your CL correctly then you only handle the scenario when we are single stepping from an LL instruction. This definitely not solving the issue when an we setting a breakpoint in the middle of an atomic sequence and then try to continue from there while it is preventing the user from doing an instruction level debugging of the atomic sequences.

I would be more happy with the following functionalities (not necessarily implementing all edge case for the first iteration):

• Step instruction behaves as it did before (1 instruction, ignores the atomic sequence)
• If we continue from a breakpoint placed inside an atomic sequence then we put back the breakpoint only after we left the atomic sequence

Please let me know what do you think.

P.S.: Have you hit any issue regarding atomic sequences during regular debugging? I would be interested about a usecase when they are affecting the debug experience so we can target the problematic point.

[jingham]

IIUC, what you are doing here is when lldb-server gets a "step instruction" request that would step into one of these atomic regions, it sets a bunch of breakpoints on it's end (not telling the LLDB stepping machinery what is going on), and continues till it hits one of these. Then it will end up not where the thread plans expect it to at all, but presumably they will just have to cope?

That doesn't seem the right way to go about this, since it means that you can't do any reasoning based on what the stepping machinery was trying to achieve.
It would be better to wire this into the ThreadPlanStepRange's AddNextRangeBreakpoint. That's where we are doing "I want to make the next step within this range". Usually we just run to the next branch, setting breakpoints to do that. Or we single step if we are on a branch. But there's no reason that's the only thing we can do here.

This would be much better because we could decide whether to do this (because we are source line stepping) or not (because we are instruction stepping) etc. We could also do things like warn if the compiler accidentally puts a line break in the middle of an atomic region.

This would make the kind of considerations Tamas mentioned possible, whereas if you do things behind the stepping machinery's back, we're can't do this, and will probably end up confused in other ways as well.

[bhushan]

In MIPS, we can not put a breakpoint in middle of an atomic sequence.
If we do so (and that breakpoint is hit) then continuing from breakpoint address will cause "SC" to fail due to a breakpoint exception.
SC fails when there’s been any exception serviced since the LL. This will then become a "never ending" sequence.

Similarly when doing assembly level debugging of an atomic sequence if we step only 1 instruction (as we are debugging assembly code)
we will end up putting breakpoint on next instruction (within atomic sequence) and will cause "SC" to fail because of reason mentioned above.

That means an atomic sequence, starting with LL and ending with SC needs to be treated as a "single instruction block".

[tberghammer]

In D17535#360519, @bhushan wrote:

In MIPS, we can not put a breakpoint in middle of an atomic sequence.
If we do so (and that breakpoint is hit) then continuing from breakpoint address will cause "SC" to fail due to a breakpoint exception.
SC fails when there’s been any exception serviced since the LL. This will then become a "never ending" sequence.

I agree that we shouldn't put a breakpoint in the middle of an atomic sequence (same is true on arm/aarch64) but your patch isn't preventing LLDB from doing it. I think what Jim and I are asking for is a solution where the atomic sequences are handled on host side so we either ensure that we don't set a breakpoint inside them or gracefully handle the continuing from them (with removing the breakpoint and only putting it back after the "SC" succeeded in the next iteration).

Similarly when doing assembly level debugging of an atomic sequence if we step only 1 instruction (as we are debugging assembly code)
we will end up putting breakpoint on next instruction (within atomic sequence) and will cause "SC" to fail because of reason mentioned above.

I expect that if somebody debug some atomic instruction sequences at assemply level then they will know about the behavior of LL and SC and they will work around the limitation with putting a breakpoint after SC to exit the loop around the atomic sequence. For me as a user it would be worrying if an instruction single step steps more then 1 actual instruction. Additionally we can add a new step command what steps out from an atomic sequence if there is user need for it.

That means an atomic sequence, starting with LL and ending with SC needs to be treated as a "single instruction block".

Agree, but I think we should do it on the host side.

[jingham]

Yes, exactly.

Jim

packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/Makefile

+LEVEL = ../../make
+
+CXX_SOURCES := main.cpp
+
+include $(LEVEL)/Makefile.rules

packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/TestStepInAtomicSequence.py

+"""
+Test to single step from atomic sequence
+"""
+
+from __future__ import print_function
+
+import os, time
+import re
+import unittest2
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+class StepInAtomicSequenceAPITestCase(TestBase):
+
+    mydir = TestBase.compute_mydir(__file__)
+
+    @skipIf(archs=no_match(re.compile('mips*')))
+    def test(self):
+        self.build()
+        exe = os.path.join(os.getcwd(), "a.out")
+        self.expect("file " + exe,
+                    patterns = [ "Current executable set to .*a.out.*" ])
+        
+        # Create a target by the debugger.
+        target = self.dbg.CreateTarget(exe)
+        self.assertTrue(target, VALID_TARGET)
+
+        breakpoint = target.BreakpointCreateByName('main', 'a.out')
+        self.assertTrue(breakpoint and
+                        breakpoint.GetNumLocations() == 1,
+                        VALID_BREAKPOINT)
+
+        # Now launch the process, and do not stop at entry point.
+        process = target.LaunchSimple (None, None, self.get_process_working_directory())
+        self.assertTrue(process, PROCESS_IS_VALID)
+
+        threads = lldbutil.get_threads_stopped_at_breakpoint(process, breakpoint)
+        self.assertEqual(len(threads), 1)
+        self.thread = threads[0]
+
+        arch = self.getArchitecture()
+        if re.match("mips" , arch):
+            atomic_seq_start_opcodes = ["ll", "lld"]
+            atomic_seq_end_opcodes = ["sc", "scd"]
+        else:
+            # TODO please add your arch here
+            self.fail('unimplemented for arch = "{arch}"'.format(arch=self.getArchitecture()))
+        
+        self.atomic_start_insns = atomic_seq_start_opcodes
+        self.atomic_end_insns = atomic_seq_end_opcodes
+
+        list = target.FindFunctions('main', lldb.eFunctionNameTypeAuto)
+        self.assertTrue(list.GetSize() == 1)
+        sc = list.GetContextAtIndex(0)
+        self.assertTrue(sc.GetSymbol().GetName() == "main")
+        function = sc.GetFunction()
+        self.assertTrue(function)
+        self.function(function, target)
+
+    def function (self, function, target):
+        """Stop at start of atomic sequence and single step"""
+        # Get the list of all instructions in the function
+        insts = function.GetInstructions(target)
+        print(insts)
+        i = 0
+        for inst in insts:
+            inst_opcode = inst.GetMnemonic(target)
+            if inst_opcode in self.atomic_start_insns:
+                # Get the address of instruction starting atomic sequence
+                start_of_seq = inst.GetAddress().GetLoadAddress(target)
+
+                # We have found starting instruction of atomic sequence
+                # now scan more instructions to find end of atomic sequence
+                # Assume that no atomic sequence is longer than 16 instructions
+                for j in range(1,16):
+                    next_inst = insts.GetInstructionAtIndex(i+j)
+                    next_inst_opcode = next_inst.GetMnemonic(target)
+                    if next_inst_opcode in self.atomic_end_insns:
+                        end_of_seq = next_inst.GetAddress().GetLoadAddress(target)
+                        break
+
+                # Stop at start of atomic sequence
+                self.thread.RunToAddress(start_of_seq)
+
+                # Step one instruction
+                self.thread.StepInstruction(False)
+
+                # Get the PC after single step
+                frame = self.thread.GetFrameAtIndex(0)
+                current_pc = frame.GetPC()
+
+                print ("Sequence Starts at 0x%x:"% start_of_seq)
+                print ("Sequence ends at 0x%x:"% end_of_seq)
+                print ("After step stopped at 0x%x:"% current_pc)
+
+                # Check if single step have skipped entire atomic sequence
+                self.assertTrue(current_pc > end_of_seq)
+                i += 1
+            else:
+                i += 1
+
+if __name__ == '__main__':
+    import atexit
+    lldb.SBDebugger.Initialize()
+    atexit.register(lambda: lldb.SBDebugger.Terminate())
+    unittest2.main()

packages/Python/lldbsuite/test/functionalities/single_step_atomic_sequence/main.cpp

+#include <atomic>
+using namespace std;
+
+std::atomic<int>  ai;
+ 
+int  tst_val= 4;
+int  new_val= 5;
+bool exchanged= false;
+ 
+int main()
+{
+    ai= 3;
+ 
+    // tst_val != ai   ==>  tst_val is modified
+    exchanged= ai.compare_exchange_strong( tst_val, new_val );
+ 
+    // tst_val == ai   ==>  ai is modified
+    exchanged= ai.compare_exchange_strong( tst_val, new_val );
+ 
+    return 0;
+}

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

typedef struct
         bool (EmulateInstructionMIPS64::*callback) (llvm::MCInst& insn);
         const char *insn_name;
     }  MipsOpcode;
     
     static MipsOpcode*
     GetOpcodeForInstruction (const char *op_name);
 
     bool
+    IsBranch (llvm::MCInst& insn);
+
+    bool
+    GetInstructionAtAddress (lldb::addr_t insn_addr, llvm::MCInst& mc_insn);
+
+    void
+    AddBreakPointAddress (lldb::addr_t bp_addr);
+
+    bool
+    WriteBreakPointAddresses ();
+
+    bool
     Emulate_DADDiu (llvm::MCInst& insn);
 
     bool
     Emulate_SD (llvm::MCInst& insn);
 
     bool
     Emulate_LD (llvm::MCInst& insn);
 
     bool
     Emulate_LDST_Imm (llvm::MCInst& insn);
 
     bool
     Emulate_LDST_Reg (llvm::MCInst& insn);
 
     bool
+    Emulate_LL (llvm::MCInst& insn);
+
+    bool
     Emulate_BXX_3ops (llvm::MCInst& insn);
 
     bool
     Emulate_BXX_3ops_C (llvm::MCInst& insn);
 
     bool
     Emulate_BXX_2ops (llvm::MCInst& insn);
 

 
 private:
     std::unique_ptr<llvm::MCDisassembler>   m_disasm;
     std::unique_ptr<llvm::MCSubtargetInfo>  m_subtype_info;
     std::unique_ptr<llvm::MCRegisterInfo>   m_reg_info;
     std::unique_ptr<llvm::MCAsmInfo>        m_asm_info;
     std::unique_ptr<llvm::MCContext>        m_context;
     std::unique_ptr<llvm::MCInstrInfo>      m_insn_info;
+    bool                                    m_auto_advance_pc;
+    lldb::addr_t                            m_atomic_seq_start;
+    lldb::addr_t                            m_atomic_seq_end;
+    uint32_t                                m_bytes_from_atomic_seq_start;
+    std::vector<lldb::addr_t>               m_breakpoint_addresses;
 };
 
 #endif // EmulateInstructionMIPS64_h_

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

#endif
     m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features));
     assert (m_asm_info.get() && m_subtype_info.get());
 
     m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
     assert (m_context.get());
 
     m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context));
     assert (m_disasm.get());
+
+    m_auto_advance_pc = false;
+    m_atomic_seq_start = 0;
+    m_atomic_seq_end = 0;
+    m_bytes_from_atomic_seq_start = 0;
 }
 
 void
 EmulateInstructionMIPS64::Initialize ()
 {
     PluginManager::RegisterPlugin (GetPluginNameStatic (),
                                    GetPluginDescriptionStatic (),
                                    CreateInstance);
g_opcodes[] =
         { "LDR",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LDR   rt, offset(base)" },
         { "LLD",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LLD   rt, offset(base)" },
         { "LDC2",       &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LDC2  rt, offset(base)" },
         { "LDXC1",      &EmulateInstructionMIPS64::Emulate_LDST_Reg,          "LDXC1 fd, index (base)" },
         { "LH",         &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LH    rt, offset(base)" },
         { "LHE",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LHE   rt, offset(base)" },
         { "LHU",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LHU   rt, offset(base)" },
         { "LHUE",       &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LHUE  rt, offset(base)" },
-        { "LL",         &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LL    rt, offset(base)" },
+        { "LL",         &EmulateInstructionMIPS64::Emulate_LL,                "LL    rt, offset(base)" },
+        { "LLD",        &EmulateInstructionMIPS64::Emulate_LL,                "LLD   rt, offset(base)" },
         { "LLE",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LLE   rt, offset(base)" },
         { "LUXC1",      &EmulateInstructionMIPS64::Emulate_LDST_Reg,          "LUXC1 fd, index (base)" },
         { "LW",         &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LW    rt, offset(rs)"   },
         { "LWC1",       &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LWC1  ft, offset(base)" },
         { "LWC2",       &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LWC2  rt, offset(base)" },
         { "LWE",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LWE   rt, offset(base)" },
         { "LWL",        &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LWL   rt, offset(base)" },
         { "LWLE",       &EmulateInstructionMIPS64::Emulate_LDST_Imm,          "LWLE  rt, offset(base)" },
if (success)
         m_opcode.SetOpcode32 (ReadMemoryUnsigned (read_inst_context, m_addr, 4, 0, &success), GetByteOrder());
     }
     if (!success)
         m_addr = LLDB_INVALID_ADDRESS;
     return success;
 }
 
 bool
+EmulateInstructionMIPS64::IsBranch (llvm::MCInst& insn)
+{
+    return m_insn_info->get(insn.getOpcode()).isBranch();
+}
+
+bool
+EmulateInstructionMIPS64::GetInstructionAtAddress (lldb::addr_t insn_addr, llvm::MCInst& mc_insn)
+{
+    DataExtractor data;
+    Opcode  opcode;
+    uint64_t insn_size;
+    bool success = false;
+    
+    Context read_inst_context;
+    read_inst_context.type = eContextReadOpcode;
+    read_inst_context.SetNoArgs ();
+    
+    opcode.SetOpcode32 (ReadMemoryUnsigned (read_inst_context, insn_addr, 4, 0, &success), GetByteOrder());
+
+    if (!success)
+        return false;
+    
+    // Get mc_insn
+    if (opcode.GetData (data))
+    {
+        llvm::MCDisassembler::DecodeStatus decode_status;
+        llvm::ArrayRef<uint8_t> raw_insn (data.GetDataStart(), data.GetByteSize());
+
+        decode_status = m_disasm->getInstruction (mc_insn, insn_size, raw_insn, insn_addr, llvm::nulls(), llvm::nulls());
+
+        if (decode_status == llvm::MCDisassembler::Success)
+            return true;
+    }
+    return false;
+}
+
+void
+EmulateInstructionMIPS64::AddBreakPointAddress (lldb::addr_t bp_addr)
+{
+    // Do not add duplicate addresses
+    if (std::find(m_breakpoint_addresses.begin(), m_breakpoint_addresses.end(), bp_addr) == m_breakpoint_addresses.end())
+    {
+        m_breakpoint_addresses.push_back(bp_addr);
+    }
+}
+
+bool
+EmulateInstructionMIPS64::WriteBreakPointAddresses ()
+{
+    Context bad_vaddr_context;
+    bad_vaddr_context.type = eContextInvalid;
+
+    if (!m_breakpoint_addresses.empty())
+    {
+        for (const auto addr: m_breakpoint_addresses)
+        {
+            // skip breakpoint placed in atomic sequence
+            if (addr > m_atomic_seq_start && addr <= m_atomic_seq_end)
+                continue;
+            if (!WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_pc_mips, addr))
+                return false;
+        }
+    }
+
+    return true;
+}
+
+bool
 EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options)
 {
     bool success = false;
     llvm::MCInst mc_insn;
     uint64_t insn_size;
     DataExtractor data;
 
     /* Keep the complexity of the decode logic with the llvm::MCDisassembler class. */
EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options)
 
     /*
      * Decoding has been done already. Just get the call-back function
      * and emulate the instruction.
     */
     MipsOpcode *opcode_data = GetOpcodeForInstruction (op_name);
 
     if (opcode_data == NULL)
-        return false;
 
     uint64_t old_pc = 0, new_pc = 0;
-    const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
+    m_auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
 
-    if (auto_advance_pc)
+    if (m_auto_advance_pc)
     {
         old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
         if (!success)
             return false;
     }
 
     /* emulate instruction */
     success = (this->*opcode_data->callback) (mc_insn);
     if (!success)
         return false;
 
-    if (auto_advance_pc)
+    if (m_auto_advance_pc)
     {
         new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
         if (!success)
             return false;
 
         /* If we haven't changed the PC, change it here */
         if (old_pc == new_pc)
         {
EmulateInstructionMIPS64::Emulate_BXX_3ops (llvm::MCInst& insn)
     rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
     rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
     offset = insn.getOperand(2).getImm();
 
     pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
     if (!success)
         return false;
 
+    // Consider branch instructions in atomic sequence.
+    if (m_atomic_seq_start)
+    {
+        target = pc + offset + m_bytes_from_atomic_seq_start;
+        AddBreakPointAddress ((lldb::addr_t)target);
+        return true;
+    }
+
     rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
     if (!success)
         return false;
 
     rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
     if (!success)
         return false;
 
EmulateInstructionMIPS64::Emulate_BXX_2ops (llvm::MCInst& insn)
 
     rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
     offset = insn.getOperand(1).getImm();
 
     pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
     if (!success)
         return false;
 
+    // Consider branch instructions in atomic sequence.
+    if (m_atomic_seq_start)
+    {
+        target = pc + offset;
+        AddBreakPointAddress ((lldb::addr_t)target);
+        return true;
+    }
+
     rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
     if (!success)
         return false;
 
     if (!strcasecmp (op_name, "BLTZL") ||
         !strcasecmp (op_name, "BLTZ"))
     {
         if (rs_val < 0)
EmulateInstructionMIPS64::Emulate_BXX_3ops_C (llvm::MCInst& insn)
     rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
     rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
     offset = insn.getOperand(2).getImm();
 
     pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
     if (!success)
         return false;
 
+    // Consider branch instructions in atomic sequence.
+    if (m_atomic_seq_start)
+    {
+        target = pc + offset + 4;
+        AddBreakPointAddress ((lldb::addr_t)target);
+        return true;
+    }
+
     rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
     if (!success)
         return false;
 
     rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success);
     if (!success)
         return false;
 
EmulateInstructionMIPS64::Emulate_BXX_2ops_C (llvm::MCInst& insn)
 
     rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
     offset = insn.getOperand(1).getImm();
 
     pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success);
     if (!success)
         return false;
 
+    // Consider branch instructions in atomic sequence.
+    if (m_atomic_seq_start)
+    {
+        target = pc + offset + 4;
+        AddBreakPointAddress ((lldb::addr_t)target);
+        return true;
+    }
+
     rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success);
     if (!success)
         return false;
 
     if (!strcasecmp (op_name, "BLTZC"))
     {
         if (rs_val < 0)
             target = pc + 4 + offset;
EmulateInstructionMIPS64::Emulate_LDST_Reg (llvm::MCInst& insn)
     address = address + index_address;
 
     /* Set the bad_vaddr register with base address used in the instruction */
     bad_vaddr_context.type = eContextInvalid;
     WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address);
 
     return true;
 }
+
+bool
+EmulateInstructionMIPS64::Emulate_LL (llvm::MCInst& insn)
+{
+    // Emulate this instruction only for single step
+    if (!m_auto_advance_pc)
+        return true;
+
+    bool success = false;
+    uint32_t atomic_sequence_length = 16;   // Assume that no atomic sequence is longer than 16 instructions.
+    lldb::addr_t insn_addr = m_addr;
+    
+    // Mark start of atomic sequence
+    m_atomic_seq_start = insn_addr;
+
+    for (uint32_t insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
+    {
+        llvm::MCInst mc_insn;
+        insn_addr = insn_addr + 4;
+        
+        // Get the instruction
+        success = GetInstructionAtAddress (insn_addr, mc_insn);
+        if (!success)
+            return false;
+
+        // Keep the track of how much bytes we have come from LL instruction.
+        m_bytes_from_atomic_seq_start += 4;
+
+        const char *op_name = m_insn_info->getName (mc_insn.getOpcode ());
+
+        // Check if it is branch instruction.
+        if (IsBranch (mc_insn))
+        {
+            MipsOpcode *opcode_data = GetOpcodeForInstruction (op_name);
+            if (opcode_data != NULL)
+            {
+                /* Let the existing emulation function do the PC write */
+                success = (this->*opcode_data->callback) (mc_insn);
+            }
+        }
+        else
+        {
+            if (!strcasecmp (op_name, "SC") ||
+                !strcasecmp (op_name, "SCD"))
+            {
+                // SC/SCD is the end of atomic sequence, add breakpoint at next instruction.
+                AddBreakPointAddress (insn_addr + 4);
+                // Address of sc/scd instruction
+                m_atomic_seq_end = insn_addr;
+                break;
+            }
+        }
+    }
+    
+    // Place the breakpoints If and only if we found end of atomic sequence.
+    if (m_atomic_seq_end)
+        WriteBreakPointAddresses ();
+
+    // Reset the counters
+    m_atomic_seq_start = 0;
+    m_atomic_seq_end = 0;
+    m_bytes_from_atomic_seq_start = 0;
+    m_breakpoint_addresses.clear();
+
+    return true;
+}

source/Plugins/Process/Linux/NativeProcessLinux.h

private:
         LazyBool m_supports_mem_region;
         std::vector<MemoryRegionInfo> m_mem_region_cache;
         Mutex m_mem_region_cache_mutex;
 
         lldb::tid_t m_pending_notification_tid;
 
         // List of thread ids stepping with a breakpoint with the address of
         // the relevan breakpoint
-        std::map<lldb::tid_t, lldb::addr_t> m_threads_stepping_with_breakpoint;
+        std::multimap<lldb::tid_t, lldb::addr_t> m_threads_stepping_with_breakpoint;
 
         /// @class LauchArgs
         ///
         /// @brief Simple structure to pass data to the thread responsible for
         /// launching a child process.
         struct LaunchArgs
         {
             LaunchArgs(Module *module,

source/Plugins/Process/Linux/NativeProcessLinux.cpp

 
 struct EmulatorBaton
 {
     NativeProcessLinux* m_process;
     NativeRegisterContext* m_reg_context;
 
     // eRegisterKindDWARF -> RegsiterValue
     std::unordered_map<uint32_t, RegisterValue> m_register_values;
+    std::vector<lldb::addr_t> next_pc_addresses;
 
     EmulatorBaton(NativeProcessLinux* process, NativeRegisterContext* reg_context) :
             m_process(process), m_reg_context(reg_context) {}
 };
 
 } // anonymous namespace
 
 static size_t

 WriteRegisterCallback (EmulateInstruction *instruction,
                        void *baton,
                        const EmulateInstruction::Context &context,
                        const RegisterInfo *reg_info,
                        const RegisterValue &reg_value)
 {
     EmulatorBaton* emulator_baton = static_cast<EmulatorBaton*>(baton);
     emulator_baton->m_register_values[reg_info->kinds[eRegisterKindDWARF]] = reg_value;
+    if (reg_info->kinds[eRegisterKindGeneric] == LLDB_REGNUM_GENERIC_PC)
+    {
+        emulator_baton->next_pc_addresses.push_back(reg_value.GetAsUInt64());
+    }
     return true;
 }
 
 static size_t
 WriteMemoryCallback (EmulateInstruction *instruction,
                      void *baton,
                      const EmulateInstruction::Context &context, 
                      lldb::addr_t addr, 
NativeProcessLinux::SetupSoftwareSingleStepping(NativeThreadLinux &thread)
 
     bool emulation_result = emulator_ap->EvaluateInstruction(eEmulateInstructionOptionAutoAdvancePC);
 
     const RegisterInfo* reg_info_pc = register_context_sp->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
     const RegisterInfo* reg_info_flags = register_context_sp->GetRegisterInfo(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS);
 
     auto pc_it = baton.m_register_values.find(reg_info_pc->kinds[eRegisterKindDWARF]);
     auto flags_it = baton.m_register_values.find(reg_info_flags->kinds[eRegisterKindDWARF]);
+    const auto arch_machine = m_arch.GetMachine();
 
     lldb::addr_t next_pc;
     lldb::addr_t next_flags;
     if (emulation_result)
     {
         assert(pc_it != baton.m_register_values.end() && "Emulation was successfull but PC wasn't updated");
         next_pc = pc_it->second.GetAsUInt64();
 
NativeProcessLinux::SetupSoftwareSingleStepping(NativeThreadLinux &thread)
     else
     {
         // The instruction emulation failed after it modified the PC. It is an
         // unknown error where we can't continue because the next instruction is
         // modifying the PC but we don't  know how.
         return Error ("Instruction emulation failed unexpectedly.");
     }
 
-    if (m_arch.GetMachine() == llvm::Triple::arm)
+    if (baton.next_pc_addresses.empty())
+    {
+        baton.next_pc_addresses.push_back(next_pc);
+    }
+
+    if (arch_machine == llvm::Triple::arm)
     {
         if (next_flags & 0x20)
         {
             // Thumb mode
             error = SetSoftwareBreakpoint(next_pc, 2);
         }
         else
         {
             // Arm mode
             error = SetSoftwareBreakpoint(next_pc, 4);
         }
     }
-    else if (m_arch.GetMachine() == llvm::Triple::mips64
-            || m_arch.GetMachine() == llvm::Triple::mips64el
-            || m_arch.GetMachine() == llvm::Triple::mips
-            || m_arch.GetMachine() == llvm::Triple::mipsel)
-        error = SetSoftwareBreakpoint(next_pc, 4);
+    else if (arch_machine == llvm::Triple::mips64 ||
+             arch_machine == llvm::Triple::mips64el ||
+             arch_machine == llvm::Triple::mips ||
+             arch_machine == llvm::Triple::mipsel)
+    {
+        for (const auto addr: baton.next_pc_addresses)
+        {
+            error = SetSoftwareBreakpoint(addr, 4);
+            if (error.Fail())
+                return error;
+        }
+    }
     else
     {
         // No size hint is given for the next breakpoint
         error = SetSoftwareBreakpoint(next_pc, 0);
     }
 
     if (error.Fail())
         return error;
 
-    m_threads_stepping_with_breakpoint.insert({thread.GetID(), next_pc});
+    for (const auto addr: baton.next_pc_addresses)
+    {
+         m_threads_stepping_with_breakpoint.insert({thread.GetID(), addr});
+    }
+
+    baton.next_pc_addresses.clear();
 
     return Error();
 }
 
 bool
 NativeProcessLinux::SupportHardwareSingleStepping() const
 {
     if (m_arch.GetMachine() == llvm::Triple::arm