Tests added.
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- rL LLVM
Event Timeline
test/MC/AMDGPU/ds.s | ||
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10 ↗ | (On Diff #48000) | Why are there now VI checks here and in most of this test file? |
test/MC/AMDGPU/ds.s | ||
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10 ↗ | (On Diff #48000) | Typo: I meant: Why are there *no* VI checks ... |
test/MC/AMDGPU/ds.s | ||
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10 ↗ | (On Diff #48000) | Literally answering, because the creator of that file didn't add those. This patch is intended to fix two specific cases (ds_write_b32 and ds_read2_b32), so I didn't bothered myself to add more VI test cases. As far as I see now, you want to have those, so I will do and update the patch. |
Ok, that's fine then. Based on the commit summary I thought you had fixed the encoding for all DS instruction and not just a few. I don't mind if you add the VI tests in a follow on patch. I'll commit this one.
BTW it really fixes all DS insns, but I had only two proven encodings on hand. The testcases I am going to add just register existing implementation (encoding looks valid but not thoroughly checked).