[X86] Update test cases that would be affected when X86FixupBWInsts is turned on.

[kbsmith1]

Summary

This updates a small number of lit tests that will be affected when X86FixupBWInsts is turned on by default. This simply
uses the internal switch to be sure to disable that optimization for these specific tests, so that they continue to test what they
are expecting to test.

[spatel]

This feels similar to D12656, and I don't think it's the right choice for the same reasons that were cited in that review.

I'd prefer that we just change the checks in these tests as part of flipping/removing the "-fixup-byte-word-insts" switch. Alternatively, we could add another RUN to these tests to show the exact codegen difference produced by -fixup-byte-word-insts for these cases.

Masking the default output could hide codegen differences that we would actually like to observe. As an example, we may want to limit the FixupBW pass based on micro-arch (should an in-order CPU get the same set of transforms as as OoO?). If that happens, then these tests become more important as verification that the default behavior is not changing.

[kbsmith1]

In D17173#351515, @spatel wrote:

This feels similar to D12656, and I don't think it's the right choice for the same reasons that were cited in that review.

I'd prefer that we just change the checks in these tests as part of flipping/removing the "-fixup-byte-word-insts" switch. Alternatively, we could add another RUN to these tests to show the exact codegen difference produced by -fixup-byte-word-insts for these cases.

Masking the default output could hide codegen differences that we would actually like to observe. As an example, we may want to limit the FixupBW pass based on micro-arch (should an in-order CPU get the same set of transforms as as OoO?). If that happens, then these tests become more important as verification that the default behavior is not changing.

I think that having additional RUN commands that show what the results should be in the presence of fixup-byte-word-insts would be OK, although many of the checks would be the same and therefore simply duplicated, making the tests harder to maintain. I think that using the option to turn off this transformation does the best job of leaving these tests as good unit tests of what they were intended to unit test, and that we should be adding specific tests as needed to adequately unit tests fixup-byte-word-inst option. I think this is different than D12656 in that I am not changing the patterns to allow "either" movw/movzwl (for example), and so these tests continue to have very specific expected output results. Due to the inability to have MachineIR specific unit tests, this seems like a very reasonable way to continue to have existing unit tests work as expected. If both you and Quentin disagree with my position on this specific change, I'll abandon it, but I think doing so dilutes the value of these tests as unit tests.

[spatel]

In D17173#351613, @kbsmith1 wrote:

Due to the inability to have MachineIR specific unit tests, this seems like a very reasonable way to continue to have existing unit tests work as expected.

Kevin,
I don't know if this changes anything, but there is some support for checking MachineIR via the -stop-after and -start-before options to llc. I used it in the /test/CodeGen/X86/machine-combiner-int.ll regression test to verify that machine operands are dead. There are probably better examples in other regression tests.

2008-06-13-NotVolatileLoadStore.ll

-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -fixup-byte-word-insts=0 | FileCheck %s
 ; These transforms are turned off for load volatiles and stores.
 ; Check that they weren't turned off for all loads and stores!
 ; CHECK-LABEL: f:
 ; CHECK-NOT: movsd
 ; CHECK: movw
 ; CHECK: addw
 
 @atomic = global double 0.000000e+00    ; <double*> [#uses=1]

MergeConsecutiveStores.ll

-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -addr-sink-using-gep=1 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=0 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=0 -addr-sink-using-gep=1 < %s | FileCheck %s
 
 %struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 }
 %struct.B = type { i32, i32, i32, i32, i32, i32, i32, i32 }
 
 ; CHECK-LABEL: merge_const_store:
 ; save 1,2,3 ... as one big integer.
 ; CHECK: movabsq $578437695752307201
 ; CHECK: ret

avx512bw-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
-; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw -fixup-byte-word-insts=0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=knl -mattr=+avx512bw -fixup-byte-word-insts=0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
 
 define i64 @test_pcmpeq_b(<64 x i8> %a, <64 x i8> %b) {
 ; AVX512BW-LABEL: test_pcmpeq_b:
 ; AVX512BW:       ## BB#0:
 ; AVX512BW-NEXT:    vpcmpeqb %zmm1, %zmm0, %k0
 ; AVX512BW-NEXT:    kmovq %k0, %rax
 ; AVX512BW-NEXT:    retq
 ;

half.ll

-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false \
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false -fixup-byte-word-insts=0 \
 ; RUN:   | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false \
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false -fixup-byte-word-insts=0 \
 ; RUN:    | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C
 
 define void @test_load_store(half* %in, half* %out) {
 ; CHECK-LABEL: test_load_store:
 ; CHECK: movw (%rdi), [[TMP:%[a-z0-9]+]]
 ; CHECK: movw [[TMP]], (%rsi)
   %val = load half, half* %in
   store half %val, half* %out

merge-store-partially-alias-loads.ll

 ; REQUIRES: asserts
-; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
-; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
+; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -fixup-byte-word-insts=0 < %s | FileCheck -check-prefix=X86 %s
+; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -fixup-byte-word-insts=0 -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
 
 ; It's OK to merge the load / store of the first 2 components, but
 ; they must not be placed on the same chain after merging.
 
 ; X86-LABEL: {{^}}merge_store_partial_overlap_load:
 ; X86-DAG: movw ([[BASEREG:%[a-z]+]]), [[LO2:%[a-z]+]]
 ; X86-DAG: movb 2([[BASEREG]]), [[HI1:%[a-z]+]]
 

return-ext.ll

-; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -fixup-byte-word-insts=0 -mtriple=i686-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -fixup-byte-word-insts=0 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 
 @x = common global i32 0, align 4
 
 define zeroext i1 @unsigned_i1() {
 entry:
   %0 = load i32, i32* @x
   %cmp = icmp eq i32 %0, 42

store-narrow.ll

 ; rdar://7860110
-; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
-; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32
+; RUN: llc -fixup-byte-word-insts=0 -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
+; RUN: llc -fixup-byte-word-insts=0 -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.2"
 
 define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
 entry:
   %A = load i32, i32* %a0, align 4
   %B = and i32 %A, -256     ; 0xFFFFFF00
   %C = zext i8 %a1 to i32