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Differential D17122

Enable beneficial Kryo CPU features
AbandonedPublic

Authored by mcrosier on Feb 10 2016, 7:30 PM.

Details

Reviewers
cestes
apazos

Diff Detail

Repository
rL LLVM

Event Timeline

apazos updated this revision to Diff 47581.Feb 10 2016, 7:30 PM
apazos retitled this revision from to Enable beneficial Kryo CPU features.
apazos updated this object.
apazos added reviewers: mcrosier, cestes.
apazos set the repository for this revision to rL LLVM.
mcrosier commandeered this revision.Feb 11 2016, 6:34 AM
mcrosier edited reviewers, added: apazos; removed: mcrosier.
rengolin added a subscriber: rengolin.Feb 11 2016, 12:49 PM

I think these can go into the other patch.

mcrosier abandoned this revision.Feb 11 2016, 12:55 PM
In D17122#350544, @rengolin wrote:

I think these can go into the other patch.

I'll merge everything into one large patch.

mcrosier mentioned this in D17162: [AArch64] Add support for Qualcomm Kryo CPU..Feb 11 2016, 1:10 PM

Revision Contents

Diff 47581

lib/Target/AArch64/AArch64ISelLowering.cpp

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} }
// Prefer likely predicted branches to selects on out-of-order cores. // Prefer likely predicted branches to selects on out-of-order cores.
if (Subtarget->isCortexA57()) if (Subtarget->isCortexA57() || Subtarget->isKryo())
PredictableSelectIsExpensive = true; PredictableSelectIsExpensive = true;
} }
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lib/Target/AArch64/AArch64InstrInfo.cpp

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// FIXME: this implementation should be micro-architecture dependent, so a // FIXME: this implementation should be micro-architecture dependent, so a
// micro-architecture target hook should be introduced here in future. // micro-architecture target hook should be introduced here in future.
bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const { bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53()) if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53() &&
!Subtarget.isKryo())
return MI->isAsCheapAsAMove(); return MI->isAsCheapAsAMove();
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
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lib/Target/AArch64/AArch64Subtarget.h

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bool isExynosM1() const { return CPUString == "exynos-m1"; } bool isExynosM1() const { return CPUString == "exynos-m1"; }
bool isKryo() const { return CPUString == "kryo"; } bool isKryo() const { return CPUString == "kryo"; }
bool useAA() const override { return isCortexA53(); } bool useAA() const override { return isCortexA53() || isKryo(); }
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call. /// that still makes it profitable to inline the call.
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lib/Target/AArch64/AArch64TargetTransformInfo.cpp

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} }
unsigned AArch64TTIImpl::getMaxInterleaveFactor(unsigned VF) { unsigned AArch64TTIImpl::getMaxInterleaveFactor(unsigned VF) {
if (ST->isCortexA57()) if (ST->isCortexA57() || ST->isKryo())
return 4; return 4;
return 2; return 2;
} }
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