[AArch64] Refactoring findMatchingStore() in aarch64-ldst-opt; NFC

[mcrosier]

Summary

This change makes findMatchingStore() follow the same coding style introduced in r260275.

[junbuml]

Since the iterator (MBBI) decreased first in the for loop, this code already handle the case when the matching store is the first instruction in the block. However, this change makes the loop follow the same coding style introduced in r260275. I will commit it after running correct tests.

[mcrosier]

Thanks for the clarification, Jun. Sounds good.

[mcrosier]

Also, my testing indicated there was no changes in Spec200X, which should be the case given the patch is a NFC... (despite my misunderstanding).

llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

if (mayAlias(MIa, MIb, TII))
       return true;
 
   return false;
 }
 
 bool AArch64LoadStoreOpt::findMatchingStore(
     MachineBasicBlock::iterator I, unsigned Limit,
     MachineBasicBlock::iterator &StoreI) {
-  MachineBasicBlock::iterator E = I->getParent()->begin();
+  MachineBasicBlock::iterator B = I->getParent()->begin();
   MachineBasicBlock::iterator MBBI = I;
   MachineInstr *LoadMI = I;
   unsigned BaseReg = getLdStBaseOp(LoadMI).getReg();
 
+  // If the load is the first instruction in the block, there's obviously
+  // not any matching store.
+  if (MBBI == B)
+    return false;
+
   // Track which registers have been modified and used between the first insn
   // and the second insn.
   ModifiedRegs.reset();
   UsedRegs.reset();
 
-  // FIXME: We miss the case where the matching store is the first instruction
-  // in the basic block.
-  for (unsigned Count = 0; MBBI != E && Count < Limit;) {
+  unsigned Count = 0;
+  do {
     --MBBI;
     MachineInstr *MI = MBBI;
-    // Skip DBG_VALUE instructions. Otherwise debug info can affect the
-    // optimization by changing how far we scan.
-    if (MI->isDebugValue())
-      continue;
-    // Now that we know this is a real instruction, count it.
+
+    // Don't count DBG_VALUE instructions towards the search limit.
+    if (!MI->isDebugValue())
       ++Count;
 
     // If the load instruction reads directly from the address to which the
     // store instruction writes and the stored value is not modified, we can
     // promote the load. Since we do not handle stores with pre-/post-index,
     // it's unnecessary to check if BaseReg is modified by the store itself.
     if (MI->mayStore() && isMatchingStore(LoadMI, MI) &&
         BaseReg == getLdStBaseOp(MI).getReg() &&
         isLdOffsetInRangeOfSt(LoadMI, MI) &&
do {
     // Otherwise, if the base register is modified, we have no match, so
     // return early.
     if (ModifiedRegs[BaseReg])
       return false;
 
     // If we encounter a store aliased with the load, return early.
     if (MI->mayStore() && mayAlias(LoadMI, MI, TII))
       return false;
-  }
+  } while (MBBI != B && Count < Limit);
   return false;
 }
 
 // Returns true if these two opcodes can be merged or paired.  Otherwise,
 // returns false.
 static bool canMergeOpc(unsigned OpcA, unsigned OpcB, LdStPairFlags &Flags) {
   // Opcodes match: nothing more to check.
   if (OpcA == OpcB)