[AArch64] Refactoring aarch64-ldst-opt. NCF.

[junbuml]

Summary

Remove narrow load / store instructions from getMatchingPairOpcode(),
and add getMatchingWideOpcode().

[mcrosier]

LGTM.

[junbuml]

Landed in r259914.

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

case AArch64::LDRSHWui:
     return AArch64::LDRHHui;
   case AArch64::LDURSBWi:
     return AArch64::LDURBBi;
   case AArch64::LDURSHWi:
     return AArch64::LDURHHi;
   }
 }
 
+static unsigned getMatchingWideOpcode(unsigned Opc) {
+  switch (Opc) {
+  default:
+    llvm_unreachable("Opcode has no wide equivalent!");
+  case AArch64::STRBBui:
+    return AArch64::STRHHui;
+  case AArch64::STRHHui:
+    return AArch64::STRWui;
+  case AArch64::STURBBi:
+    return AArch64::STURHHi;
+  case AArch64::STURHHi:
+    return AArch64::STURWi;
+  case AArch64::LDRHHui:
+  case AArch64::LDRSHWui:
+    return AArch64::LDRWui;
+  case AArch64::LDURHHi:
+  case AArch64::LDURSHWi:
+    return AArch64::LDURWi;
+  case AArch64::LDRBBui:
+  case AArch64::LDRSBWui:
+    return AArch64::LDRHHui;
+  case AArch64::LDURBBi:
+  case AArch64::LDURSBWi:
+    return AArch64::LDURHHi;
+  }
+}
+
 static unsigned getMatchingPairOpcode(unsigned Opc) {
   switch (Opc) {
   default:
     llvm_unreachable("Opcode has no pairwise equivalent!");
   case AArch64::STRSui:
   case AArch64::STURSi:
     return AArch64::STPSi;
   case AArch64::STRDui:
   case AArch64::STURDi:
     return AArch64::STPDi;
   case AArch64::STRQui:
   case AArch64::STURQi:
     return AArch64::STPQi;
-  case AArch64::STRBBui:
-    return AArch64::STRHHui;
-  case AArch64::STRHHui:
-    return AArch64::STRWui;
-  case AArch64::STURBBi:
-    return AArch64::STURHHi;
-  case AArch64::STURHHi:
-    return AArch64::STURWi;
   case AArch64::STRWui:
   case AArch64::STURWi:
     return AArch64::STPWi;
   case AArch64::STRXui:
   case AArch64::STURXi:
     return AArch64::STPXi;
   case AArch64::LDRSui:
   case AArch64::LDURSi:
     return AArch64::LDPSi;
   case AArch64::LDRDui:
   case AArch64::LDURDi:
     return AArch64::LDPDi;
   case AArch64::LDRQui:
   case AArch64::LDURQi:
     return AArch64::LDPQi;
   case AArch64::LDRWui:
   case AArch64::LDURWi:
     return AArch64::LDPWi;
   case AArch64::LDRXui:
   case AArch64::LDURXi:
     return AArch64::LDPXi;
   case AArch64::LDRSWui:
   case AArch64::LDURSWi:
     return AArch64::LDPSWi;
-  case AArch64::LDRHHui:
-  case AArch64::LDRSHWui:
-    return AArch64::LDRWui;
-  case AArch64::LDURHHi:
-  case AArch64::LDURSHWi:
-    return AArch64::LDURWi;
-  case AArch64::LDRBBui:
-  case AArch64::LDRSBWui:
-    return AArch64::LDRHHui;
-  case AArch64::LDURBBi:
-  case AArch64::LDURSBWi:
-    return AArch64::LDURHHi;
   }
 }
 
 static unsigned isMatchingStore(MachineInstr *LoadInst,
                                 MachineInstr *StoreInst) {
   unsigned LdOpc = LoadInst->getOpcode();
   unsigned StOpc = StoreInst->getOpcode();
   switch (LdOpc) {
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
 
   int SExtIdx = Flags.getSExtIdx();
   unsigned Opc =
       SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
   bool IsUnscaled = isUnscaledLdSt(Opc);
   int OffsetStride = IsUnscaled ? getMemScale(I) : 1;
 
   bool MergeForward = Flags.getMergeForward();
-  unsigned NewOpc = getMatchingPairOpcode(Opc);
   // Insert our new paired instruction after whichever of the paired
   // instructions MergeForward indicates.
   MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
   // Also based on MergeForward is from where we copy the base register operand
   // so we get the flags compatible with the input code.
   const MachineOperand &BaseRegOp =
       MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
 
if (isNarrowLoad(Opc)) {
     MachineInstr *RtNewDest = MergeForward ? I : Paired;
     // When merging small (< 32 bit) loads for big-endian targets, the order of
     // the component parts gets swapped.
     if (!Subtarget->isLittleEndian())
       std::swap(RtMI, Rt2MI);
     // Construct the new load instruction.
     MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
     NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
-                       TII->get(NewOpc))
+                       TII->get(getMatchingWideOpcode(Opc)))
                    .addOperand(getLdStRegOp(RtNewDest))
                    .addOperand(BaseRegOp)
                    .addImm(OffsetImm)
                    .setMemRefs(I->mergeMemRefsWith(*Paired));
 
     DEBUG(
         dbgs()
         << "Creating the new load and extract. Replacing instructions:\n    ");
AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
   MachineInstrBuilder MIB;
   if (isNarrowStore(Opc)) {
     // Change the scaled offset from small to large type.
     if (!IsUnscaled) {
       assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
       OffsetImm /= 2;
     }
     MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
-                  TII->get(NewOpc))
+                  TII->get(getMatchingWideOpcode(Opc)))
               .addOperand(getLdStRegOp(I))
               .addOperand(BaseRegOp)
               .addImm(OffsetImm)
               .setMemRefs(I->mergeMemRefsWith(*Paired));
   } else {
     // Scale the immediate offset, if necessary.
     if (isUnscaledLdSt(RtMI->getOpcode())) {
       assert(!(OffsetImm % getMemScale(RtMI)) &&
              "Offset should be a multiple of the stride!");
       OffsetImm /= getMemScale(RtMI);
     }
     MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
-                  TII->get(NewOpc))
+                  TII->get(getMatchingPairOpcode(Opc)))
               .addOperand(getLdStRegOp(RtMI))
               .addOperand(getLdStRegOp(Rt2MI))
               .addOperand(BaseRegOp)
               .addImm(OffsetImm);
   }
 
   (void)MIB;
 
AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
   if (IsNarrowStore && Reg != AArch64::WZR)
     return E;
 
   // Early exit if the first instruction modifies the base register.
   // e.g., ldr x0, [x0]
   if (FirstMI->modifiesRegister(BaseReg, TRI))
     return E;
 
-  // Early exit if the offset if not possible to match. (6 bits of positive
+  // Early exit if the offset is not possible to match. (6 bits of positive
   // range, plus allow an extra one in case we find a later insn that matches
   // with Offset-1)
   int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
   if (!(isNarrowLoad(Opc) || IsNarrowStore) &&
       !inBoundsForPair(IsUnscaled, Offset, OffsetStride))
     return E;
 
   // Track which registers have been modified and used between the first insn
bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
   //    with bitfield extract instructions.
   //      e.g.,
   //        ldrh w0, [x2]
   //        ldrh w1, [x2, #2]
   //        ; becomes
   //        ldr w0, [x2]
   //        ubfx w1, w0, #16, #16
   //        and w0, w0, #ffff
+  //
+  //    Also merge adjacent zero stores into a wider store.
+  //      e.g.,
+  //        strh wzr, [x0]
+  //        strh wzr, [x0, #2]
+  //        ; becomes
+  //        str wzr, [x0]
   for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
        enableNarrowLdOpt && MBBI != E;) {
     MachineInstr *MI = MBBI;
     switch (MI->getOpcode()) {
     default:
       // Just move on to the next instruction.
       ++MBBI;
       break;