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AMDGPU/SI: Promote i1 SETCC operations
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Authored by tstellarAMD on Jan 15 2016, 10:49 AM.

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Summary

While working on uniform branching, I've hit a few cases where we emit
i1 SETCC operations.

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tstellarAMD retitled this revision from to AMDGPU/SI: Promote i1 SETCC operations.
tstellarAMD updated this object.
tstellarAMD added a reviewer: arsenm.
tstellarAMD added a subscriber: llvm-commits.
arsenm edited edge metadata.Jan 15 2016, 10:57 AM

From the testcase, I don't see why promotion would be necessary here

From the testcase, I don't see why promotion would be necessary here

The basic block order is swapped by SelectionDAG, so an i1 xor is inserted before the branch instruction. This is optimized to an i1 setcc instruction by the DAGCombine. This isn't an issue now, because SIISelLowering::LowerBRCOND was folding these into the branch intrinsic, but it will be an issue when we switch to uniform branching.

From the testcase, I don't see why promotion would be necessary here

The basic block order is swapped by SelectionDAG, so an i1 xor is inserted before the branch instruction. This is optimized to an i1 setcc instruction by the DAGCombine. This isn't an issue now, because SIISelLowering::LowerBRCOND was folding these into the branch intrinsic, but it will be an issue when we switch to uniform branching.

Can you swap the block order and insert the xor here for the same effect so the DAG builder doesn't do this?

tstellarAMD edited edge metadata.

Put explicit i1 xor in test case.

arsenm accepted this revision.Jan 19 2016, 12:47 PM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jan 19 2016, 12:47 PM
This revision was automatically updated to reflect the committed changes.