[mips] Fix RetCC_MipsN to promote types smaller than i64 to GPR-width.

[vkalintiris]

Summary

In order to avoid a number of redundant sign/zero-extensions, we have
to custom combine AssertSext on our target and fold a generic pattern
in the target independent DAG combiner for the SIGN_EXTEND_INREG node.

Depends on D10970

[dsanders]

Well caught. It turns out we've been falling through to the O32 handler in some cases.

There's a few changes that don't look right to me and I've commented on these below. I'd like to explain one set of the comments in advance. Up until select-flt.ll I've pointed out a number of redundant instructions. These look like regressions but it's possible that we've always emitted some of them and have just not mentioned them in the test. Could you check whether these are regressions or not?

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6934–6935 ↗

(On Diff #44983)

I think we can do better here. We really want to know whether the sign bit that sext_in_reg will replicate is any one of the sign-bits that ComputeNumSignBits reports so I believe the condition should be:

(N00VTBits - N00NSB) < EVTBits

In any case I'd suggest posting this as a separate patch without the '[mips]' tag since this affects all targets.

lib/Target/Mips/MipsCallingConv.td

183–185

Putting this here prevents the big-endian CCIfInReg path on line 205 from occurring. As a result small structs won't return correctly.

I think it belongs on line 206 at which point the little-endian CCIfInReg case could be folded into it

344

Could you also make this conditional on isABI_O32()? We'd have caught this sooner if we hadn't fallen out into the O32 implementation.

lib/Target/Mips/MipsISelLowering.cpp

825–826

What is 'asext'? I assume it's 'AssertSExt' but it's confusing when we already have 'aext' for any extend. Also, could you clarify which 'asext' you're referring to at the end of the sentence?

829–830

Optional: Would 'Outer' make more sense than 'Old'?

836

Isn't it always a trunc because NewVT has fewer bits than OldVT?

test/CodeGen/Mips/atomic.ll

100

Why did you remove the signext's from these tests?

test/CodeGen/Mips/llvm-ir/ashr.ll

43–59

indentation. Similarly below.

43–59

Something is odd here. The two GP32 cases don't sign-extend but the two GP64 cases do. None of them need to sign-extend because there's no way for ashr to remove the sign extension that was already present in the 'i8 signext' argument. Similarly below

Also, the andi instructions are still redundant because srav only reads the lowest 5 bits. Please restore the fixme.

117–132

Please restore the MIPS32R6 case.

120–123

Why did you remove the definition of the $[[BB1]] label?

179–181

Why did you remove the definition of the $[[BB1]] label?

test/CodeGen/Mips/llvm-ir/lshr.ll

80

This sign extend is redundant. The srlv already did it

test/CodeGen/Mips/llvm-ir/mul.ll

145–154

These three sign extends are redundant. For the M4 case, the mflo already did it and for the other two it was the mul

test/CodeGen/Mips/llvm-ir/ret.ll

121

I doubt you meant 'GP32' here.

Also why are the GP32 and GP64 cases different now?

test/CodeGen/Mips/llvm-ir/sdiv.ll

6–10

The prefixes contradict each other

21–26

The prefixes contradict each other

74–78

This is not correct for R6. This kind of divide instruction was removed from the ISA.

100–105

This is not correct for R6. This kind of divide instruction was removed from the ISA.

123–133

The two sll's are redundant. The mflo's already did it

test/CodeGen/Mips/llvm-ir/select-flt.ll

1

Regarding the splitting of select.ll: This is a good thing but it makes it difficult to see what's changed. Could we split it and change it in separate commits? Feel free to commit the split part of this without further review.

37

This andi and the similar ones below are redundant because %s can only be 0 or -1 and the branch test is for zero/not-zero

test/CodeGen/Mips/llvm-ir/srem.ll

73–78

Like in the div.ll test, this isn't correct for R6. Similarly below.

[vkalintiris]

Addressed Daniel's comments.

As far as I can tell, almost all of our redundant sign-extensions come from the
usage of the 32-bit version of our instructions.

[vkalintiris]

lib/Target/Mips/MipsCallingConv.td

183–185

I don't think that the small structs case in big-endian is affected by this. Here's the relevant generated code:

if (LocVT == MVT::i1 ||                                                         
    LocVT == MVT::i8 ||                                                         
    LocVT == MVT::i16 ||                                                        
    LocVT == MVT::i32) {                                                        
  LocVT = MVT::i64;                                                             
  if (ArgFlags.isSExt())                                                        
      LocInfo = CCValAssign::SExt;                                              
  else if (ArgFlags.isZExt())                                                   
      LocInfo = CCValAssign::ZExt;                                              
  else                                                                          
      LocInfo = CCValAssign::AExt;                                              
}                                                                               
                                                                                
if (LocVT == MVT::i64) {                                                        
  if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) {          
    if (!RetCC_F128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))             
      return false;                                                             
  }                                                                             
}                                                                               
                                                                                
if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
  if (LocVT == MVT::i8 ||                                                       
      LocVT == MVT::i16 ||                                                      
      LocVT == MVT::i32 ||                                                      
      LocVT == MVT::i64) {                                                      
    if (ArgFlags.isInReg()) {                                                   
      LocVT = MVT::i64;                                                         
      if (ArgFlags.isSExt())                                                    
              LocInfo = CCValAssign::SExt;                                      
      else if (ArgFlags.isZExt())                                               
              LocInfo = CCValAssign::ZExt;                                      
      else                                                                      
              LocInfo = CCValAssign::AExt;                                      
    }                                                                           
  }                                                                             
}                                                                               
                                                                                
if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
  if (LocVT == MVT::i8 ||                                                       
      LocVT == MVT::i16 ||                                                      
      LocVT == MVT::i32 ||                                                      
      LocVT == MVT::i64) {                                                      
    if (ArgFlags.isInReg()) {                                                   
      LocVT = MVT::i64;                                                         
      if (ArgFlags.isSExt())                                                    
              LocInfo = CCValAssign::SExtUpper;                                 
      else if (ArgFlags.isZExt())                                               
              LocInfo = CCValAssign::ZExtUpper;                                 
      else                                                                      
              LocInfo = CCValAssign::AExtUpper;                                 
    }                                                                           
  }                                                                             
}

However, we can merge together this change with the small structs case, for little-endian, if we don't want to handle this explicitly.

344

This causes the 35 new failures shown below. Should I add a FIXME instead?

CodeGen/Mips/2008-07-16-SignExtInReg.ll
CodeGen/Mips/atomic.ll                 
CodeGen/Mips/cconv/return-float.ll     
CodeGen/Mips/cconv/return.ll           
CodeGen/Mips/cmov.ll                   
CodeGen/Mips/const-mult.ll             
CodeGen/Mips/countleading.ll           
CodeGen/Mips/ctlz-v.ll                 
CodeGen/Mips/cttz-v.ll                 
CodeGen/Mips/divrem.ll                 
CodeGen/Mips/fcmp.ll                   
CodeGen/Mips/llvm-ir/add.ll            
CodeGen/Mips/llvm-ir/and.ll            
CodeGen/Mips/llvm-ir/ashr.ll           
CodeGen/Mips/llvm-ir/call.ll           
CodeGen/Mips/llvm-ir/indirectbr.ll     
CodeGen/Mips/llvm-ir/load-atomic.ll    
CodeGen/Mips/llvm-ir/lshr.ll           
CodeGen/Mips/llvm-ir/mul.ll            
CodeGen/Mips/llvm-ir/or.ll             
CodeGen/Mips/llvm-ir/ret.ll            
CodeGen/Mips/llvm-ir/sdiv.ll           
CodeGen/Mips/llvm-ir/select.ll         
CodeGen/Mips/llvm-ir/shl.ll            
CodeGen/Mips/llvm-ir/srem.ll           
CodeGen/Mips/llvm-ir/sub.ll            
CodeGen/Mips/llvm-ir/udiv.ll           
CodeGen/Mips/llvm-ir/urem.ll           
CodeGen/Mips/llvm-ir/xor.ll            
CodeGen/Mips/load-store-left-right.ll  
CodeGen/Mips/mips64-f128.ll            
CodeGen/Mips/octeon_popcnt.ll          
CodeGen/Mips/select.ll                 
CodeGen/Mips/tailcall.ll               
CodeGen/Mips/zeroreg.ll

lib/Target/Mips/MipsISelLowering.cpp

836

You are right it's always a trunc. I though that getSExtOrTrunc() is just a convenience function.

test/CodeGen/Mips/atomic.ll

100

Because we generate an extra pair of dsll/dsra at the NO-SEB_SEH label. MipsISelLowering::emitAtomicBinaryPartword() uses only the 32-bit version of the instructions. The sll/sra instructions get emitted by that function and the dsll/dsra promote the result to i64. The review request D13649 tries to solve a similar problem for MipsTargetLowering::emitAtomicCmpSwapPartword().

test/CodeGen/Mips/llvm-ir/ashr.ll

43–59

For GP32 the initial DAG:

  t11: i8 = sra t7, t17   
t12: i32 = sign_extend t11

is transformed into:

  t19: i32 = sra t18, t17                        
t20: i32 = sign_extend_inreg t19, ValueType:ch:i8

after the initial type legalization. For GP64, the initial DAG:

t16: i8 = sra t12, t15
t17: i32 = sign_extend t16
  t18: i64 = sign_extend t16

is transformed into:

  t16: i8 = sra t28, t23
t18: i64 = sign_extend t16

However, after the second pass, we get a sext_inreg that "remembers" the original type (i8):

    t31: i32 = sra t29, t23
  t32: i64 = any_extend t31
t33: i64 = sign_extend_inreg t32, ValueType:ch:i8

Otherwise, we would get a simple 32 -> 64 bit extension as is the case with ashr_i32().

test/CodeGen/Mips/llvm-ir/lshr.ll

80

The correspondent ISD::SRL node is legalized to i32:

  t10: i32 = srl t5, t9
t11: i64 = sign_extend t10

test/CodeGen/Mips/llvm-ir/mul.ll

145–154

Similarly with the lshr.ll case the ISD::MUL is legalized to i32:

t10: i32 = mul t5, t9

t11: i64 = sign_extend t10

test/CodeGen/Mips/llvm-ir/ret.ll

121

Because with the changes of this patch, we are materializing an i64 and we consult MipsAnalyzeImmediate in order to get the instruction(s) we need (see D16290 for more info).

test/CodeGen/Mips/llvm-ir/sdiv.ll

74–78

The label should have been R2-R5. I fixed this.

123–133

We'll have to change the way we handle MFLO because we use it's 32-bit version:

%vreg4<def> = PseudoSDIV %vreg0:sub_32<kill>, %vreg1:sub_32; ACC64:%vreg4 GPR64:%vreg0,%vreg1
TEQ %vreg1:sub_32<kill>, %ZERO, 7; GPR64:%vreg1
%vreg5<def> = PseudoMFLO %vreg4<kill>; GPR32:%vreg5 ACC64:%vreg4
%vreg6<def> = SLL64_32 %vreg5<kill>; GPR64:%vreg6 GPR32:%vreg5

test/CodeGen/Mips/llvm-ir/select-flt.ll

37

The problem is in PromoteTargetBoolean(). It blindly calls getExtendForContent(), which returns the correct target-specific action, without considering any information from DAG's ComputeNumSignBits first. Should I add a FIXME?

lib/Target/Mips/MipsCallingConv.td

CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
                                       T0_64, T1_64, T2_64, T3_64]>>,
 
   // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
   CCIfType<[f32], CCAssignToStack<4, 8>>,
   CCIfType<[i64, f64], CCAssignToStack<8, 8>>
 ]>;
 
 def RetCC_MipsN : CallingConv<[
+  // Promote i1/i8/i16/i32 arguments to i64
+  CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
+
   // f128 needs to be handled similarly to f32 and f64. However, f128 is not
   // legal and is lowered to i128 which is further lowered to a pair of i64's.
   // This presents us with a problem for the calling convention since hard-float
   // still needs to pass them in FPU registers, and soft-float needs to use $v0,
   // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
   // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
   // whether the result was originally an f128 into the tablegen-erated code.
   //

 //===----------------------------------------------------------------------===//
 // Mips Calling Convention Dispatch
 //===----------------------------------------------------------------------===//
 
 def RetCC_Mips : CallingConv<[
   CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
   CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
   CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
   CCDelegateTo<RetCC_MipsO32>
 ]>;
 
 def CC_Mips_ByVal : CallingConv<[
   CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
   CCIfByVal<CCPassByVal<8, 8>>
 ]>;
 
 def CC_Mips16RetHelper : CallingConv<[

lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   setTargetDAGCombine(ISD::SDIVREM);
   setTargetDAGCombine(ISD::UDIVREM);
   setTargetDAGCombine(ISD::SELECT);
   setTargetDAGCombine(ISD::AND);
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::ADD);
+  setTargetDAGCombine(ISD::AssertSext);
 
   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
 
   // The arguments on the stack are defined in terms of 4-byte slots on O32
   // and 8-byte slots on N32/N64.
   setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
 
   setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
   EVT ValTy = N->getValueType(0);
   SDLoc DL(N);
 
   SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
                              Add.getOperand(0));
   return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
 }
 
+static SDValue performAssertSextCombine(SDNode *N, SelectionDAG &DAG,
+                                        TargetLowering::DAGCombinerInfo &DCI,
+                                        const MipsSubtarget &Subtarget) {
+  SDValue N0 = N->getOperand(0);
+  EVT NewVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+
+  // fold (AssertSext (trunc (AssertSext x) -> (trunc (AssertSext x))
+  // if the type of the extension of the innermost AssertSext node is
+  // smaller from that of the outermost node, eg:
+  // (AssertSext (trunc:i32 (AssertSext:i64 x, i8)), i32) ->
+  //                                              (trunc (AssertSext x, i8))
+  if (N0.getOpcode() == ISD::TRUNCATE &&
+      N0.getOperand(0).getOpcode() == ISD::AssertSext) {
+    SDValue OuterAssertSext = N0.getOperand(0);
+    EVT OuterVT = cast<VTSDNode>(OuterAssertSext->getOperand(1))->getVT();
+
+    if (NewVT.bitsLT(OuterVT)) {
+      SDValue NewAssertSext =
+          DAG.getNode(ISD::AssertSext, SDLoc(N), OuterAssertSext.getValueType(),
+                      OuterAssertSext.getOperand(0), DAG.getValueType(NewVT));
+      return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), NewAssertSext);
+    }
+  }
+
+  return SDValue();
+}
+
 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
   const {
   SelectionDAG &DAG = DCI.DAG;
   unsigned Opc = N->getOpcode();
 
   switch (Opc) {
   default: break;
   case ISD::SDIVREM:
   case ISD::UDIVREM:
     return performDivRemCombine(N, DAG, DCI, Subtarget);
   case ISD::SELECT:
     return performSELECTCombine(N, DAG, DCI, Subtarget);
   case MipsISD::CMovFP_F:
   case MipsISD::CMovFP_T:
     return performCMovFPCombine(N, DAG, DCI, Subtarget);
   case ISD::AND:
     return performANDCombine(N, DAG, DCI, Subtarget);
   case ISD::OR:
     return performORCombine(N, DAG, DCI, Subtarget);
   case ISD::ADD:
     return performADDCombine(N, DAG, DCI, Subtarget);
+  case ISD::AssertSext:
+    return performAssertSextCombine(N, DAG, DCI, Subtarget);
   }
 
   return SDValue();
 }
 
 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
   return Subtarget.hasMips32();
 }

test/CodeGen/Mips/atomic.ll

 ; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
 ; ALL:       $[[BB1]]:
 }
 
 
 
 @y = common global i8 0, align 1
 
-define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
+define i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
 entry:
   %0 = atomicrmw add i8* @y, i8 %incr monotonic
   ret i8 %0
 
 ; ALL-LABEL: AtomicLoadAdd8:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(

 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]
 }
 
-define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
+define i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
 entry:
   %0 = atomicrmw sub i8* @y, i8 %incr monotonic
   ret i8 %0
 
 ; ALL-LABEL: AtomicLoadSub8:
 
 ; MIPS32-ANY: lw      $[[R0:[0-9]+]], %got(y)
 ; MIPS64-ANY: ld      $[[R0:[0-9]+]], %got_disp(y)(

 ; ALL:        srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH: sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH: sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:seb     $2, $[[R16]]
 }
 
-define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
+define i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
 entry:
   %0 = atomicrmw nand i8* @y, i8 %incr monotonic
   ret i8 %0
 
 ; ALL-LABEL: AtomicLoadNand8:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(

 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]
 }
 
-define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
+define i8 @AtomicSwap8(i8 signext %newval) nounwind {
 entry:
   %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
   ret i8 %0
 
 ; ALL-LABEL: AtomicSwap8:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(

 
 ; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]
 
 }
 
-define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
+define i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
 entry:
   %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
   %0 = extractvalue { i8, i1 } %pair0, 0
   ret i8 %0
 
 ; ALL-LABEL: AtomicCmpSwap8:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)

 
 ; ALL:           xor     $[[R20:[0-9]+]], $[[R19]], $5
 ; ALL:           sltiu   $2, $[[R20]], 1
 }
 
 ; Check one i16 so that we cover the seh sign extend
 @z = common global i16 0, align 1
 
-define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
+define i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
 entry:
   %0 = atomicrmw add i16* @z, i16 %incr monotonic
   ret i16 %0
 
 ; ALL-LABEL: AtomicLoadAdd16:
 
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(z)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(z)(

test/CodeGen/Mips/cconv/return.ll

 ; know if this is correct.
 
 @byte = global i8 zeroinitializer
 @word = global i32 zeroinitializer
 @dword = global i64 zeroinitializer
 @float = global float zeroinitializer
 @double = global double zeroinitializer
 
-define i8 @reti8() nounwind {
+define signext i8 @reti8() nounwind {
 entry:
         %0 = load volatile i8, i8* @byte
         ret i8 %0
 }
 
 ; ALL-LABEL: reti8:
 ; O32-DAG:           lui [[R1:\$[0-9]+]], %hi(byte)
-; O32-DAG:           lbu $2, %lo(byte)([[R1]])
+; O32-DAG:           lb  $2, %lo(byte)([[R1]])
 ; N32-DAG:           lui [[R1:\$[0-9]+]], %hi(byte)
-; N32-DAG:           lbu $2, %lo(byte)([[R1]])
+; N32-DAG:           lb  $2, %lo(byte)([[R1]])
 ; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(byte)(
-; N64-DAG:           lbu $2, 0([[R1]])
+; N64-DAG:           lb  $2, 0([[R1]])
 
-define i32 @reti32() nounwind {
+define signext i32 @reti32() nounwind {
 entry:
         %0 = load volatile i32, i32* @word
         ret i32 %0
 }
 
 ; ALL-LABEL: reti32:
 ; O32-DAG:           lui [[R1:\$[0-9]+]], %hi(word)
 ; O32-DAG:           lw $2, %lo(word)([[R1]])
 ; N32-DAG:           lui [[R1:\$[0-9]+]], %hi(word)
-; N32-DAG:           lw $2, %lo(word)([[R1]])
+; N32-DAG:           lw  [[R2:\$[0-9]+]], %lo(word)([[R1]])
+; N32-DAG:           sll $2, [[R2]], 0
 ; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(word)(
-; N64-DAG:           lw $2, 0([[R1]])
+; N64-DAG:           lw  [[R2:\$[0-9]+]], 0([[R1]])
+; N64-DAG:           sll $2, [[R2]], 0
 
-define i64 @reti64() nounwind {
+define signext i64 @reti64() nounwind {
 entry:
         %0 = load volatile i64, i64* @dword
         ret i64 %0
 }
 
 ; ALL-LABEL: reti64:
 ; On O32, we must use v0 and v1 for the return value
 ; O32-DAG:           lw $2, %lo(dword)([[R1:\$[0-9]+]])
 ; O32-DAG:           addiu [[R2:\$[0-9]+]], [[R1]], %lo(dword)
 ; O32-DAG:           lw $3, 4([[R2]])
 ; N32-DAG:           ld $2, %lo(dword)([[R1:\$[0-9]+]])
 ; N64-DAG:           ld  [[R1:\$[0-9]+]], %got_disp(dword)([[R1:\$[0-9]+]])
 ; N64-DAG:           ld $2, 0([[R1]])

test/CodeGen/Mips/delay-slot-kill.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
-; We have to XFAIL this temporarily because of the reversion of r229675.
-; XFAIL: *
 
 ; Currently, the following IR assembly generates a KILL instruction between
 ; the bitwise-and instruction and the return instruction. We verify that the
 ; delay slot filler ignores such KILL instructions by filling the slot of the
 ; return instruction properly.
 define signext i32 @f1(i32 signext %a, i32 signext %b) {
 entry:
   ; CHECK:          jr      $ra
   ; CHECK-NEXT:     and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r
 }

test/CodeGen/Mips/fcmp.ll

 
 define i32 @oeq_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: oeq_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
-; FIXME: The sign extension below is redundant.
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    dmfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    sll $[[T2:[0-9]+]], $[[T1]], 0
-; 64-CMP-DAG:    andi $2, $[[T2]], 1
+; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ogt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ogt_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @oge_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: oge_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @olt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: olt_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ole_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ole_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @one_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: one_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ord_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ueq_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ugt_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ugt_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uge_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: uge_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ult_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ult_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
 
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ule_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: ule_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @une_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: une_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: uno_f32:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1

 
 define i32 @oeq_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: oeq_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oeq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ogt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ogt_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ogt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @oge_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: oge_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp oge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @olt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: olt_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp olt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ole_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ole_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ole double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @one_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: one_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp one double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ord_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ord_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp ord double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ueq_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ueq_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ueq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ugt_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ugt_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uge_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: uge_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ult_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ult_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ult double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @ule_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: ule_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1
 
   %1 = fcmp ule double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @une_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: une_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movt $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 32-CMP-DAG:    andi $2, $[[T2]], 1
 
 ; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
 ; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp une double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @uno_f64(double %a, double %b) nounwind {
 ; ALL-LABEL: uno_f64:
 
 ; 32-C-DAG:      addiu $2, $zero, 1
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; FIXME: Remove redundant sign extension.
-; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-C-DAG:      daddiu $2, $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
-; 64-C:          sll $2, $[[T0]], 0
+; 64-C:          movf $2, $zero, $fcc0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
 ; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 64-CMP-DAG:    andi $2, $[[T1]], 1

test/CodeGen/Mips/llvm-ir/add.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=ALL -check-prefix=GP32-NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=ALL -check-prefix=GP32-NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=ALL -check-prefix=GP64-NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=ALL -check-prefix=GP64-NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=ALL -check-prefix=GP64-NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 
 define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: add_i1:
 
-  ; ALL:        addu    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        sll     $[[T0]], $[[T0]], 31
-  ; ALL:        sra     $2, $[[T0]], 31
+  ; GP32:       addu    $[[T0:[0-9]+]], $4, $5
+  ; GP32:       sll     $[[T0]], $[[T0]], 31
+  ; GP32:       sra     $2, $[[T0]], 31
+
+  ; GP64:       addu    $[[T0:[0-9]+]], $4, $5
+  ; GP64:       dsll    $[[T0]], $[[T0]], 63
+  ; GP64:       dsra    $2, $[[T0]], 63
 
   %r = add i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @add_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: add_i8:
 
-  ; NOT-R2-R6:  addu    $[[T0:[0-9]+]], $4, $5
-  ; NOT-R2-R6:  sll     $[[T0]], $[[T0]], 24
-  ; NOT-R2-R6:  sra     $2, $[[T0]], 24
+  ; GP32-NOT-R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; GP32-NOT-R2-R6:      sll     $[[T0]], $[[T0]], 24
+  ; GP32-NOT-R2-R6:      sra     $2, $[[T0]], 24
+
+  ; GP64-NOT-R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-NOT-R2-R6:      dsll    $[[T0]], $[[T0]], 56
+  ; GP64-NOT-R2-R6:      dsra    $2, $[[T0]], 56
 
-  ; R2-R6:         addu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:         seb     $2, $[[T0:[0-9]+]]
+  ; R2-R6:               addu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:               seb     $2, $[[T0:[0-9]+]]
 
   %r = add i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @add_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: add_i16:
 
-  ; NOT-R2-R6:  addu    $[[T0:[0-9]+]], $4, $5
-  ; NOT-R2-R6:  sll     $[[T0]], $[[T0]], 16
-  ; NOT-R2-R6:  sra     $2, $[[T0]], 16
+  ; GP32-NOT-R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; GP32-NOT-R2-R6:      sll     $[[T0]], $[[T0]], 16
+  ; GP32-NOT-R2-R6:      sra     $2, $[[T0]], 16
+
+  ; GP64-NOT-R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-NOT-R2-R6:      dsll    $[[T0]], $[[T0]], 48
+  ; GP64-NOT-R2-R6:      dsra    $2, $[[T0]], 48
 
-  ; R2-R6:         addu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:         seh     $2, $[[T0:[0-9]+]]
+  ; R2-R6:               addu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:               seh     $2, $[[T0:[0-9]+]]
 
   %r = add i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @add_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: add_i32:
 
-  ; ALL:        addu    $2, $4, $5
+  ; GP32:       addu    $2, $4, $5
+
+  ; GP64:       addu    $[[T0:[0-9]+]], $4, $5
+  ; GP64:       sll     $2, $[[T0]], 0
 
   %r = add i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @add_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: add_i64:

test/CodeGen/Mips/llvm-ir/and.ll

; ALL-LABEL: and_i16:
   %r = and i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; GP32:         and     $2, $4, $5
-
-  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: and_i64:

test/CodeGen/Mips/llvm-ir/ashr.ll

-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=M2
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=M3
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M2 -check-prefix=GP32-NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP32-R2-R6
+
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M3 -check-prefix=GP64-NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M64R6 -check-prefix=GP64-R2-R6
 
 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i1:
 
-  ; ALL:        move    $2, $4
+  ; ALL:          move      $2, $4
 
   %r = ashr i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i8:
 
-  ; FIXME: The andi instruction is redundant.
-  ; ALL:        andi    $[[T0:[0-9]+]], $5, 255
-  ; ALL:        srav    $2, $4, $[[T0]]
+  ; FIXME: The andi instruction in the following cases is redundant.
+
+  ; GP32-NOT-R2-R6:   andi      $[[T0:[0-9]+]], $5, 255
+  ; GP32-NOT-R2-R6:   srav      $2, $4, $[[T0]]
+
+  ; GP32-R2-R6:       andi      $[[T0:[0-9]+]], $5, 255
+  ; GP32-R2-R6:       srav      $2, $4, $[[T0]]
+
+  ; GP64-NOT-R2-R6:   andi      $[[T0:[0-9]+]], $5, 255
+  ; GP64-NOT-R2-R6:   srav      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-NOT-R2-R6:   dsll      $[[T2:[0-9]+]], $[[T1]], 56
+  ; GP64-NOT-R2-R6:   dsra      $2, $[[T2]], 56
+
+  ; GP64-R2-R6:       andi      $[[T0:[0-9]+]], $5, 255
+  ; GP64-R2-R6:       srav      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-R2-R6:       seb       $2, $[[T1]]
 
   %r = ashr i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i16:
 
-  ; FIXME: The andi instruction is redundant.
-  ; ALL:        andi    $[[T0:[0-9]+]], $5, 65535
-  ; ALL:        srav    $2, $4, $[[T0]]
+  ; FIXME: The andi instruction in the following cases is redundant.
+
+  ; GP32-NOT-R2-R6:   andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP32-NOT-R2-R6:   srav      $2, $4, $[[T0]]
+
+  ; GP32-R2-R6:       andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP32-R2-R6:       srav      $2, $4, $[[T0]]
+
+  ; GP64-NOT-R2-R6:   andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP64-NOT-R2-R6:   srav      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-NOT-R2-R6:   dsll      $[[T2:[0-9]+]], $[[T1]], 48
+  ; GP64-NOT-R2-R6:   dsra      $2, $[[T2]], 48
+
+  ; GP64-R2-R6:       andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP64-R2-R6:       srav      $[[T1:[0-9]+]], $4, $[[T0]]
 
   %r = ashr i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i32:
 
-  ; ALL:        srav    $2, $4, $5
+  ; GP32-NOT-R2-R6:   srav      $2, $4, $5
+
+  ; GP32-R2-R6:       srav      $2, $4, $5
+
+  ; GP64-NOT-R2-R6:   srav      $[[T0:[0-9]+]], $4, $5
+  ; GP64-NOT-R2-R6:   sll       $2, $[[T0]], 0
+
+  ; GP64-R2-R6:       srav      $[[T0:[0-9]+]], $4, $5
+  ; GP64-R2-R6:       sll       $2, $[[T0]], 0
 
   %r = ashr i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i64:
 
-  ; M2:         srav      $[[T0:[0-9]+]], $4, $7
-  ; M2:         andi      $[[T1:[0-9]+]], $7, 32
-  ; M2:         bnez      $[[T1]], $[[BB0:BB[0-9_]+]]
-  ; M2:         move      $3, $[[T0]]
-  ; M2:         srlv      $[[T2:[0-9]+]], $5, $7
-  ; M2:         not       $[[T3:[0-9]+]], $7
-  ; M2:         sll       $[[T4:[0-9]+]], $4, 1
-  ; M2:         sllv      $[[T5:[0-9]+]], $[[T4]], $[[T3]]
-  ; M2:         or        $3, $[[T3]], $[[T2]]
-  ; M2:         $[[BB0]]:
-  ; M2:         beqz      $[[T1]], $[[BB1:BB[0-9_]+]]
-  ; M2:         nop
-  ; M2:         sra       $2, $4, 31
-  ; M2:         $[[BB1]]:
-  ; M2:         jr        $ra
-  ; M2:         nop
+  ; M2:           srav      $[[T0:[0-9]+]], $4, $7
+  ; M2:           andi      $[[T1:[0-9]+]], $7, 32
+  ; M2:           bnez      $[[T1]], $[[BB0:BB[0-9_]+]]
+  ; M2:           move      $3, $[[T0]]
+  ; M2:           srlv      $[[T2:[0-9]+]], $5, $7
+  ; M2:           not       $[[T3:[0-9]+]], $7
+  ; M2:           sll       $[[T4:[0-9]+]], $4, 1
+  ; M2:           sllv      $[[T5:[0-9]+]], $[[T4]], $[[T3]]
+  ; M2:           or        $3, $[[T5]], $[[T2]]
+  ; M2:           $[[BB0]]:
+  ; M2:           beqz      $[[T1]], $[[BB1:BB[0-9_]+]]
+  ; M2:           nop
+  ; M2:           sra       $2, $4, 31
+  ; M2:           $[[BB1]]:
+  ; M2:           jr        $ra
 
-  ; 32R1-R5:    srlv      $[[T0:[0-9]+]], $5, $7
-  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R5:    sll       $[[T2:[0-9]+]], $4, 1
-  ; 32R1-R5:    sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R5:    or        $3, $[[T3]], $[[T0]]
-  ; 32R1-R5:    srav      $[[T4:[0-9]+]], $4, $7
-  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R5:    movn      $3, $[[T4]], $[[T5]]
-  ; 32R1-R5:    sra       $4, $4, 31
-  ; 32R1-R5:    jr        $ra
-  ; 32R1-R5:    movn      $2, $4, $[[T5]]
+  ; M32R1-R5:     srlv      $[[T0:[0-9]+]], $5, $7
+  ; M32R1-R5:     not       $[[T1:[0-9]+]], $7
+  ; M32R1-R5:     sll       $[[T2:[0-9]+]], $4, 1
+  ; M32R1-R5:     sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M32R1-R5:     or        $3, $[[T3]], $[[T0]]
+  ; M32R1-R5:     srav      $[[T4:[0-9]+]], $4, $7
+  ; M32R1-R5:     andi      $[[T5:[0-9]+]], $7, 32
+  ; M32R1-R5:     movn      $3, $[[T4]], $[[T5]]
+  ; M32R1-R5:     sra       $[[T6:[0-9]+]], $4, 31
+  ; M32R1-R5:     jr        $ra
+  ; M32R1-R5:     movn      $2, $[[T6]], $[[T5]]
 
-  ; 32R6:       srav      $[[T0:[0-9]+]], $4, $7
-  ; 32R6:       andi      $[[T1:[0-9]+]], $7, 32
-  ; 32R6:       seleqz    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
-  ; 32R6:       sra       $[[T3:[0-9]+]], $4, 31
-  ; 32R6:       selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
-  ; 32R6:       or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
-  ; 32R6:       srlv      $[[T6:[0-9]+]], $5, $7
-  ; 32R6:       not       $[[T7:[0-9]+]], $7
-  ; 32R6:       sll       $[[T8:[0-9]+]], $4, 1
-  ; 32R6:       sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
-  ; 32R6:       or        $[[T10:[0-9]+]], $[[T9]], $[[T6]]
-  ; 32R6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
-  ; 32R6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
-  ; 32R6:       jr        $ra
-  ; 32R6:       or        $3, $[[T0]], $[[T11]]
+  ; 32R6:         srav      $[[T0:[0-9]+]], $4, $7
+  ; 32R6:         andi      $[[T1:[0-9]+]], $7, 32
+  ; 32R6:         seleqz    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+  ; 32R6:         sra       $[[T3:[0-9]+]], $4, 31
+  ; 32R6:         selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
+  ; 32R6:         or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
+  ; 32R6:         srlv      $[[T6:[0-9]+]], $5, $7
+  ; 32R6:         not       $[[T7:[0-9]+]], $7
+  ; 32R6:         sll       $[[T8:[0-9]+]], $4, 1
+  ; 32R6:         sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; 32R6:         or        $[[T10:[0-9]+]], $[[T9]], $[[T6]]
+  ; 32R6:         seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
+  ; 32R6:         selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
+  ; 32R6:         jr        $ra
+  ; 32R6:         or        $3, $[[T0]], $[[T11]]
 
-  ; GP64:       dsrav     $2, $4, $5
+  ; GP64-NOT-R2-R6:   dsrav     $2, $4, $5
+
+  ; GP64-R2-R6:       dsrav     $2, $4, $5
 
   %r = ashr i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i128:
 
-  ; GP32:           lw        $25, %call16(__ashrti3)($gp)
+  ; GP32:        lw         $25, %call16(__ashrti3)($gp)
 
-  ; M3:             sll       $[[T0:[0-9]+]], $7, 0
-  ; M3:             dsrav     $[[T1:[0-9]+]], $4, $7
-  ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
-  ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
-  ; M3:             move      $3, $[[T1]]
-  ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
-  ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
-  ; M3:             not       $[[T6:[0-9]+]], $[[T0]]
-  ; M3:             dsllv     $[[T7:[0-9]+]], $[[T5]], $[[T6]]
-  ; M3:             or        $3, $[[T7]], $[[T4]]
-  ; M3:             $[[BB0]]:
-  ; M3:             beqz      $[[T3]], $[[BB1:BB[0-9_]+]]
-  ; M3:             nop
-  ; M3:             dsra      $2, $4, 63
-  ; M3:             $[[BB1]]:
-  ; M3:             jr        $ra
-  ; M3:             nop
+  ; M3:          sll        $[[T0:[0-9]+]], $7, 0
+  ; M3:          dsrav      $[[T1:[0-9]+]], $4, $7
+  ; M3:          andi       $[[T2:[0-9]+]], $[[T0]], 64
+  ; M3:          bnez       $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
+  ; M3:          move       $3, $[[T1]]
+  ; M3:          dsrlv      $[[T4:[0-9]+]], $5, $7
+  ; M3:          dsll       $[[T5:[0-9]+]], $4, 1
+  ; M3:          not        $[[T6:[0-9]+]], $[[T0]]
+  ; M3:          dsllv      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; M3:          or         $3, $[[T7]], $[[T4]]
+  ; M3:          $[[BB0]]:
+  ; M3:          beqz       $[[T3]], $[[BB1:BB[0-9_]+]]
+  ; M3:          nop
+  ; M3:          dsra       $2, $4, 63
+  ; M3:          $[[BB1]]:
+  ; M3:          jr         $ra
+  ; M3:          nop
 
-  ; GP64-NOT-R6:    dsrlv     $[[T0:[0-9]+]], $5, $7
-  ; GP64-NOT-R6:    dsll      $[[T1:[0-9]+]], $4, 1
-  ; GP64-NOT-R6:    sll       $[[T2:[0-9]+]], $7, 0
-  ; GP64-NOT-R6:    not       $[[T3:[0-9]+]], $[[T2]]
-  ; GP64-NOT-R6:    dsllv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
-  ; GP64-NOT-R6:    or        $3, $[[T4]], $[[T0]]
-  ; GP64-NOT-R6:    dsrav     $2, $4, $7
-  ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
-  ; GP64-NOT-R6:    movn      $3, $2, $[[T5]]
-  ; GP64-NOT-R6:    dsra      $[[T6:[0-9]+]], $4, 63
-  ; GP64-NOT-R6:    jr        $ra
-  ; GP64-NOT-R6:    movn      $2, $[[T6]], $[[T5]]
+  ; GP64-NOT-R6: dsrlv      $[[T0:[0-9]+]], $5, $7
+  ; GP64-NOT-R6: dsll       $[[T1:[0-9]+]], $4, 1
+  ; GP64-NOT-R6: sll        $[[T2:[0-9]+]], $7, 0
+  ; GP64-NOT-R6: not        $[[T3:[0-9]+]], $[[T2]]
+  ; GP64-NOT-R6: dsllv      $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; GP64-NOT-R6: or         $3, $[[T4]], $[[T0]]
+  ; GP64-NOT-R6: dsrav      $[[R0:[0-9]+]], $4, $7
+  ; GP64-NOT-R6: andi       $[[T5:[0-9]+]], $[[T2]], 64
+  ; GP64-NOT-R6: movn       $3, $2, $[[T5]]
+  ; GP64-NOT-R6: dsra       $[[T6:[0-9]+]], $4, 63
+  ; GP64-NOT-R6: jr         $ra
+  ; GP64-NOT-R6: movn       $2, $[[T6]], $[[T5]]
 
-  ; 64R6:           dsrav     $[[T0:[0-9]+]], $4, $7
-  ; 64R6:           sll       $[[T1:[0-9]+]], $7, 0
-  ; 64R6:           andi      $[[T2:[0-9]+]], $[[T1]], 64
-  ; 64R6:           sll       $[[T3:[0-9]+]], $[[T2]], 0
-  ; 64R6:           seleqz    $[[T4:[0-9]+]], $[[T0]], $[[T3]]
-  ; 64R6:           dsra      $[[T5:[0-9]+]], $4, 63
-  ; 64R6:           selnez    $[[T6:[0-9]+]], $[[T5]], $[[T3]]
-  ; 64R6:           or        $2, $[[T6]], $[[T4]]
-  ; 64R6:           dsrlv     $[[T7:[0-9]+]], $5, $7
-  ; 64R6:           dsll      $[[T8:[0-9]+]], $4, 1
-  ; 64R6:           not       $[[T9:[0-9]+]], $[[T1]]
-  ; 64R6:           dsllv     $[[T10:[0-9]+]], $[[T8]], $[[T9]]
-  ; 64R6:           or        $[[T11:[0-9]+]], $[[T10]], $[[T7]]
-  ; 64R6:           seleqz    $[[T12:[0-9]+]], $[[T11]], $[[T3]]
-  ; 64R6:           selnez    $[[T13:[0-9]+]], $[[T0]], $[[T3]]
-  ; 64R6:           jr        $ra
-  ; 64R6:           or        $3, $[[T13]], $[[T12]]
+  ; M64R6:       dsrav      $[[T0:[0-9]+]], $4, $7
+  ; M64R6:       sll        $[[T1:[0-9]+]], $7, 0
+  ; M64R6:       andi       $[[T2:[0-9]+]], $[[T1]], 64
+  ; M64R6:       sll        $[[T3:[0-9]+]], $[[T2]], 0
+  ; M64R6:       seleqz     $[[T4:[0-9]+]], $[[T0]], $[[T3]]
+  ; M64R6:       dsra       $[[T5:[0-9]+]], $4, 63
+  ; M64R6:       selnez     $[[T6:[0-9]+]], $[[T5]], $[[T3]]
+  ; M64R6:       or         $2, $[[T6]], $[[T4]]
+  ; M64R6:       dsrlv      $[[T7:[0-9]+]], $5, $7
+  ; M64R6:       dsll       $[[T8:[0-9]+]], $4, 1
+  ; M64R6:       not        $[[T9:[0-9]+]], $[[T1]]
+  ; M64R6:       dsllv      $[[T10:[0-9]+]], $[[T8]], $[[T9]]
+  ; M64R6:       or         $[[T11:[0-9]+]], $[[T10]], $[[T7]]
+  ; M64R6:       seleqz     $[[T12:[0-9]+]], $[[T11]], $[[T3]]
+  ; M64R6:       selnez     $[[T13:[0-9]+]], $[[T0]], $[[T3]]
+  ; M64R6:       jr         $ra
+  ; M64R6:       or         $3, $[[T13]], $[[T12]]
 
   %r = ashr i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/lshr.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
 
 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i1:
 
-  ; ALL:        move    $2, $4
+  ; ALL:          move      $2, $4
 
   %r = lshr i1 %a, %b
   ret i1 %r
 }
 
 define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
 entry:
 ; ALL-LABEL: lshr_i8:
 
-  ; ALL:        srlv    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        andi    $2, $[[T0]], 255
+  ; ALL:          srlv      $[[T0:[0-9]+]], $4, $5
+  ; ALL:          andi      $2, $[[T0]], 255
 
   %r = lshr i8 %a, %b
   ret i8 %r
 }
 
 define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
 entry:
 ; ALL-LABEL: lshr_i16:
 
-  ; ALL:        srlv    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        andi    $2, $[[T0]], 65535
+  ; ALL:          srlv      $[[T0:[0-9]+]], $4, $5
+  ; ALL:          andi      $2, $[[T0]], 65535
 
   %r = lshr i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i32:
 
-  ; ALL:          srlv    $2, $4, $5
+  ; GP32:         srlv      $2, $4, $5
+
+  ; GP64:         srlv      $[[T0:[0-9]+]], $4, $5
+  ; GP64:         sll       $2, $[[T0]], 0
 
   %r = lshr i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i64:
; ALL-LABEL: lshr_i64:
   ; 32R6:       andi      $[[T5:[0-9]+]], $7, 32
   ; 32R6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T3]]
   ; 32R6:       srlv      $[[T7:[0-9]+]], $4, $7
   ; 32R6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
   ; 32R6:       or        $3, $[[T8]], $[[T6]]
   ; 32R6:       jr        $ra
   ; 32R6:       seleqz    $2, $[[T7]], $[[T5]]
 
-  ; GP64:         dsrlv   $2, $4, $5
+  ; GP64:       dsrlv     $2, $4, $5
 
   %r = lshr i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i128:
 
-  ; GP32:         lw      $25, %call16(__lshrti3)($gp)
+  ; GP32:           lw        $25, %call16(__lshrti3)($gp)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1

test/CodeGen/Mips/llvm-ir/mul.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=M2 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R1-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=32R6 -check-prefix=GP32
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=M4 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
 ; RUN:    -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
; ALL-LABEL: mul_i1:
   ; 32R1-R5:    sra     $2, $[[T0]], 31
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       sll     $[[T0]], $[[T0]], 31
   ; 32R6:       sra     $2, $[[T0]], 31
 
   ; M4:         mult    $4, $5
   ; M4:         mflo    $[[T0:[0-9]+]]
-  ; M4:         sll     $[[T0]], $[[T0]], 31
-  ; M4:         sra     $2, $[[T0]], 31
+  ; M4:         dsll    $[[T0]], $[[T0]], 63
+  ; M4:         dsra    $2, $[[T0]], 63
 
   ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R1-R5:    sll     $[[T0]], $[[T0]], 31
-  ; 64R1-R5:    sra     $2, $[[T0]], 31
+  ; 64R1-R5:    dsll    $[[T0]], $[[T0]], 63
+  ; 64R1-R5:    dsra    $2, $[[T0]], 63
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R6:       sll     $[[T0]], $[[T0]], 31
-  ; 64R6:       sra     $2, $[[T0]], 31
+  ; 64R6:       dsll    $[[T0]], $[[T0]], 63
+  ; 64R6:       dsra    $2, $[[T0]], 63
 
   %r = mul i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: mul_i8:
; ALL-LABEL: mul_i8:
   ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
   ; 32R2-R5:    seb     $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       seb     $2, $[[T0]]
 
   ; M4:         mult    $4, $5
   ; M4:         mflo    $[[T0:[0-9]+]]
-  ; M4:         sll     $[[T0]], $[[T0]], 24
-  ; M4:         sra     $2, $[[T0]], 24
+  ; M4:         dsll    $[[T0]], $[[T0]], 56
+  ; M4:         dsra    $2, $[[T0]], 56
 
   ; 64R1:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R1:       sll     $[[T0]], $[[T0]], 24
-  ; 64R1:       sra     $2, $[[T0]], 24
+  ; 64R1:       dsll    $[[T0]], $[[T0]], 56
+  ; 64R1:       dsra    $2, $[[T0]], 56
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seb     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seb     $2, $[[T0]]
   %r = mul i8 %a, %b
   ret i8 %r
; ALL-LABEL: mul_i16:
   ; 32R2-R5:    mul     $[[T0:[0-9]+]], $4, $5
   ; 32R2-R5:    seh     $2, $[[T0]]
 
   ; 32R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 32R6:       seh     $2, $[[T0]]
 
   ; M4:         mult    $4, $5
   ; M4:         mflo    $[[T0:[0-9]+]]
-  ; M4:         sll     $[[T0]], $[[T0]], 16
-  ; M4:         sra     $2, $[[T0]], 16
+  ; M4:         dsll    $[[T0]], $[[T0]], 48
+  ; M4:         dsra    $2, $[[T0]], 48
 
   ; 64R1:       mul     $[[T0:[0-9]+]], $4, $5
-  ; 64R1:       sll     $[[T0]], $[[T0]], 16
-  ; 64R1:       sra     $2, $[[T0]], 16
+  ; 64R1:       dsll    $[[T0]], $[[T0]], 48
+  ; 64R1:       dsra    $2, $[[T0]], 48
 
   ; 64R2:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R2:       seh     $2, $[[T0]]
 
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seh     $2, $[[T0]]
   %r = mul i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: mul_i32:
 
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
   ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 
-  ; 64R1-R5:    mul     $2, $4, $5
-  ; 64R6:       mul     $2, $4, $5
+  ; M4:         mult    $4, $5
+  ; M4:         mflo    $[[T0:[0-9]+]]
+  ; M4:         sll     $2, $[[T0]], 0
+
+  ; 64R1-R5:    mul     $[[T0:[0-9]+]], $4, $5
+  ; 64R1-R5:    sll     $2, $[[T0]], 0
+
+  ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
+  ; 64R6:       sll     $2, $[[T0]], 0
   %r = mul i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: mul_i64:
 
   ; M2:         mult    $4, $7

test/CodeGen/Mips/llvm-ir/or.ll

; ALL-LABEL: or_i16:
   %r = or i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
-
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          or     $2, $4, $5
 
   %r = or i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: or_i64:

test/CodeGen/Mips/llvm-ir/ret.ll

 ; Test all important variants of the 'ret' instruction.
 ;
 ; For non-void returns it is necessary to have something to return so we also
 ; test constant generation here.
 ;
 ; We'll test pointer returns in a separate file since the relocation model
 ; affects it and it's undesirable to repeat the non-pointer returns for each
 ; relocation model.
 
-; RUN: llc -march=mips   -mcpu=mips32   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips   -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
-; RUN: llc -march=mips64 -mcpu=mips4    -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64   -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
+; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR32 \
+; RUN:                 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR32 \
+; RUN:                 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR32 \
+; RUN:                 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR32 \
+; RUN:                 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR32 \
+; RUN:                 -check-prefix=MTHC1 -check-prefix=R6
+
+; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR64 \
+; RUN:                 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR64 \
+; RUN:                 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR64 \
+; RUN:                 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR64 \
+; RUN:                 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR64 \
+; RUN:                 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GPR64 \
+; RUN:                 -check-prefix=DMTC1 -check-prefix=R6
 
 define void @ret_void() {
 ; ALL-LABEL: ret_void:
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
 
   ret void

 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
 
   ret i32 65536
 }
 
 define i32 @ret_i32_65537() {
 ; ALL-LABEL: ret_i32_65537:
-; ALL:           lui $[[T0:[0-9]+]], 1
-; ALL-DAG:       ori $2, $[[T0]], 1
+
+; GP32:          lui $[[T0:[0-9]+]], 1
+; GP32-DAG:      ori $2, $[[T0]], 1
+
+; GP64:          lui $[[T0:[0-9]+]], 1
+; GP64-DAG:      daddiu $2, $[[T0]], 1
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
 
   ret i32 65537
 }
 
 define i64 @ret_i64_65537() {

test/CodeGen/Mips/llvm-ir/sdiv.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=GP32-NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=GP32-NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefix=R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-R6 -check-prefix=R6
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefix=R6 -check-prefix=64R6
+; RUN:    -check-prefix=GP64-R6 -check-prefix=R6
 
 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i1:
 
-  ; NOT-R6:       div     $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mflo    $[[T0:[0-9]+]]
+  ; GP32-NOT-R6:      div     $zero, $4, $5
+  ; GP32-NOT-R6:      teq     $5, $zero, 7
+  ; GP32-NOT-R6:      mflo    $[[T0:[0-9]+]]
   ; FIXME: The sll/sra instructions are redundant since div is signed.
-  ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; NOT-R6:       sra     $2, $[[T1]], 31
+  ; GP32-NOT-R6:      sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; GP32-NOT-R6:      sra     $2, $[[T1]], 31
 
-  ; R6:           div     $[[T0:[0-9]+]], $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP64-NOT-R6:      div     $zero, $4, $5
+  ; GP64-NOT-R6:      teq     $5, $zero, 7
+  ; GP64-NOT-R6:      mflo    $[[T0:[0-9]+]]
+  ; FIXME: The dsll/dsra instructions are redundant since div is signed.
+  ; GP64-NOT-R6:      dsll     $[[T1:[0-9]+]], $[[T0]], 63
+  ; GP64-NOT-R6:      dsra     $2, $[[T1]], 63
+
+  ; GP32-R6:          div     $[[T0:[0-9]+]], $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP32-R6:          sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; GP32-R6:          sra     $2, $[[T1]], 31
+
+  ; GP64-R6:          div     $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
   ; FIXME: The sll/sra instructions are redundant since div is signed.
-  ; R6:           sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; R6:           sra     $2, $[[T1]], 31
+  ; GP64-R6:          dsll    $[[T1:[0-9]+]], $[[T0]], 63
+  ; GP64-R6:          dsra    $2, $[[T1]], 63
 
   %r = sdiv i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i8:
 
-  ; NOT-R2-R6:    div     $zero, $4, $5
-  ; NOT-R2-R6:    teq     $5, $zero, 7
-  ; NOT-R2-R6:    mflo    $[[T0:[0-9]+]]
+  ; GP32-NOT-R2-R6:   div     $zero, $4, $5
+  ; GP32-NOT-R2-R6:   teq     $5, $zero, 7
+  ; GP32-NOT-R2-R6:   mflo    $[[T0:[0-9]+]]
   ; FIXME: The sll/sra instructions are redundant since div is signed.
-  ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
-  ; NOT-R2-R6:    sra     $2, $[[T1]], 24
+  ; GP32-NOT-R2-R6:   sll     $[[T1:[0-9]+]], $[[T0]], 24
+  ; GP32-NOT-R2-R6:   sra     $2, $[[T1]], 24
 
-  ; R2-R5:        div     $zero, $4, $5
-  ; R2-R5:        teq     $5, $zero, 7
-  ; R2-R5:        mflo    $[[T0:[0-9]+]]
+  ; R2-R5:            div     $zero, $4, $5
+  ; R2-R5:            teq     $5, $zero, 7
+  ; R2-R5:            mflo    $[[T0:[0-9]+]]
   ; FIXME: This instruction is redundant.
-  ; R2-R5:        seb     $2, $[[T0]]
+  ; R2-R5:            seb     $2, $[[T0]]
 
-  ; R6:           div     $[[T0:[0-9]+]], $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; R6:               div     $[[T0:[0-9]+]], $4, $5
+  ; R6:               teq     $5, $zero, 7
   ; FIXME: This instruction is redundant.
-  ; R6:           seb     $2, $[[T0]]
+  ; R6:               seb     $2, $[[T0]]
 
   %r = sdiv i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i16:
 
-  ; NOT-R2-R6:    div     $zero, $4, $5
-  ; NOT-R2-R6:    teq     $5, $zero, 7
-  ; NOT-R2-R6:    mflo    $[[T0:[0-9]+]]
+  ; GP32-NOT-R2-R6:   div     $zero, $4, $5
+  ; GP32-NOT-R2-R6:   teq     $5, $zero, 7
+  ; GP32-NOT-R2-R6:   mflo    $[[T0:[0-9]+]]
   ; FIXME: The sll/sra instructions are redundant since div is signed.
-  ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
-  ; NOT-R2-R6:    sra     $2, $[[T1]], 16
+  ; GP32-NOT-R2-R6:   sll     $[[T1:[0-9]+]], $[[T0]], 16
+  ; GP32-NOT-R2-R6:   sra     $2, $[[T1]], 16
 
-  ; R2-R5:        div     $zero, $4, $5
-  ; R2-R5:        teq     $5, $zero, 7
-  ; R2-R5:        mflo    $[[T0:[0-9]+]]
-  ; FIXME: This is instruction is redundant since div is signed.
-  ; R2-R5:        seh     $2, $[[T0]]
+  ; R2-R5:            div     $zero, $4, $5
+  ; R2-R5:            teq     $5, $zero, 7
+  ; R2-R5:            mflo    $[[T0:[0-9]+]]
+  ; FIXME: This instruction is redundant.
+  ; R2-R5:            seh     $2, $[[T0]]
 
-  ; R6:           div     $[[T0:[0-9]+]], $4, $5
-  ; R6:           teq     $5, $zero, 7
-  ; FIXME: This is instruction is redundant since div is signed.
-  ; R6:           seh     $2, $[[T0]]
+  ; R6:               div     $[[T0:[0-9]+]], $4, $5
+  ; R6:               teq     $5, $zero, 7
+  ; FIXME: This instruction is redundant.
+  ; R6:               seh     $2, $[[T0]]
 
   %r = sdiv i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i32:
 
-  ; NOT-R6:       div     $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mflo    $2
+  ; GP32-NOT-R6:      div     $zero, $4, $5
+  ; GP32-NOT-R6:      teq     $5, $zero, 7
+  ; GP32-NOT-R6:      mflo    $2
 
-  ; R6:           div     $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP64-NOT-R6:      div     $zero, $4, $5
+  ; GP64-NOT-R6:      teq     $5, $zero, 7
+  ; GP64-NOT-R6:      mflo    $[[T0:[0-9]+]]
+  ; GP64-NOT-R6:      sll     $2, $[[T0]], 0
+
+  ; GP32-R6:          div     $2, $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+
+  ; GP64-R6:          div     $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; GP64-R6:          sll     $2, $[[T0]], 0
 
   %r = sdiv i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i64:
 
-  ; GP32:         lw      $25, %call16(__divdi3)($gp)
+  ; GP32-NOT-R6:      lw      $25, %call16(__divdi3)($gp)
+  ; GP32-R6:          lw      $25, %call16(__divdi3)($gp)
 
-  ; GP64-NOT-R6:  ddiv    $zero, $4, $5
-  ; GP64-NOT-R6:  teq     $5, $zero, 7
-  ; GP64-NOT-R6:  mflo    $2
+  ; GP64-NOT-R6:      ddiv    $zero, $4, $5
+  ; GP64-NOT-R6:      teq     $5, $zero, 7
+  ; GP64-NOT-R6:      mflo    $2
 
-  ; 64R6:         ddiv    $2, $4, $5
-  ; 64R6:         teq     $5, $zero, 7
+  ; GP64-R6:          ddiv    $2, $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
 
   %r = sdiv i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
 entry:
   ; ALL-LABEL: sdiv_i128:
 
-    ; GP32:         lw      $25, %call16(__divti3)($gp)
+    ; GP32-NOT-R6:    lw      $25, %call16(__divti3)($gp)
+    ; GP32-R6:        lw      $25, %call16(__divti3)($gp)
 
-    ; GP64-NOT-R6:  ld      $25, %call16(__divti3)($gp)
-    ; 64R6:         ld      $25, %call16(__divti3)($gp)
+    ; GP64-NOT-R6:    ld      $25, %call16(__divti3)($gp)
+    ; GP64-R6:        ld      $25, %call16(__divti3)($gp)
 
     %r = sdiv i128 %a, %b
     ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/select-dbl.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
 define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_double:
 
-  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
-  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2:         nop
-  ; M2:         ldc1    $f0, 16($sp)
-  ; M2:         jr      $ra
-  ; M2:         nop
-  ; M2:         $[[BB0]]:
-  ; M2:         mtc1    $7, $f0
-  ; M2:         jr      $ra
-  ; M2:         mtc1    $6, $f1
+  ; M2:           andi      $[[T0:[0-9]+]], $4, 1
+  ; M2:           bnez      $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:           nop
+  ; M2:           ldc1      $f0, 16($sp)
+  ; M2:           jr        $ra
+  ; M2:           nop
+  ; M2:           $[[BB0]]:
+  ; M2:           mtc1      $7, $f0
+  ; M2:           jr        $ra
+  ; M2:           mtc1      $6, $f1
 
-  ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
-  ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
-  ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
-  ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-32:      ldc1    $f0, 16($sp)
-  ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
+  ; CMOV-32:      mtc1      $7, $[[F0:f[0-9]+]]
+  ; CMOV-32R1:    mtc1      $6, $f{{[0-9]+}}
+  ; CMOV-32R2-R5: mthc1     $6, $[[F0]]
+  ; CMOV-32:      andi      $[[T0:[0-9]+]], $4, 1
+  ; CMOV-32:      ldc1      $f0, 16($sp)
+  ; CMOV-32:      movn.d    $f0, $[[F0]], $[[T0]]
 
-  ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
-  ; SEL-32:     mthc1   $6, $[[F0]]
-  ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
-  ; SEL-32:     mtc1    $4, $f0
-  ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
+  ; SEL-32:       mtc1      $7, $[[F0:f[0-9]+]]
+  ; SEL-32:       mthc1     $6, $[[F0]]
+  ; SEL-32:       ldc1      $[[F1:f[0-9]+]], 16($sp)
+  ; SEL-32:       mtc1      $4, $f0
+  ; SEL-32:       sel.d     $f0, $[[F1]], $[[F0]]
 
-  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
-  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M3:         nop
-  ; M3:         mov.d   $f13, $f14
-  ; M3:         $[[BB0]]:
-  ; M3:         jr      $ra
-  ; M3:         mov.d   $f0, $f13
+  ; M3:           andi      $[[T0:[0-9]+]], $4, 1
+  ; M3:           bnez      $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:           nop
+  ; M3:           mov.d     $f13, $f14
+  ; M3:           $[[BB0]]:
+  ; M3:           jr        $ra
+  ; M3:           mov.d     $f0, $f13
 
-  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
-  ; CMOV-64:    mov.d   $f0, $f14
+  ; CMOV-64:      andi      $[[T0:[0-9]+]], $4, 1
+  ; CMOV-64:      movn.d    $f14, $f13, $[[T0]]
+  ; CMOV-64:      mov.d     $f0, $f14
 
-  ; SEL-64:     mtc1    $4, $f0
-  ; SEL-64:     sel.d   $f0, $f14, $f13
+  ; SEL-64:       dmtc1     $4, $f0
+  ; SEL-64:       sel.d     $f0, $f14, $f13
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_i1_double_reordered(double %x, double %y,
                                               i1 signext %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_double_reordered:
 
-  ; M2:         lw      $[[T0:[0-9]+]], 16($sp)
-  ; M2:         andi    $[[T1:[0-9]+]], $[[T0]], 1
-  ; M2:         bnez    $[[T1]], $[[BB0:BB[0-9_]+]]
-  ; M2:         nop
-  ; M2:         mov.d   $f12, $f14
-  ; M2:         $[[BB0]]:
-  ; M2:         jr      $ra
-  ; M2:         mov.d   $f0, $f12
+  ; M2:           lw        $[[T0:[0-9]+]], 16($sp)
+  ; M2:           andi      $[[T1:[0-9]+]], $[[T0]], 1
+  ; M2:           bnez      $[[T1]], $[[BB0:BB[0-9_]+]]
+  ; M2:           nop
+  ; M2:           mov.d     $f12, $f14
+  ; M2:           $[[BB0]]:
+  ; M2:           jr        $ra
+  ; M2:           mov.d     $f0, $f12
 
-  ; CMOV-32:    lw      $[[T0:[0-9]+]], 16($sp)
-  ; CMOV-32:    andi    $[[T1:[0-9]+]], $[[T0]], 1
-  ; CMOV-32:    movn.d  $f14, $f12, $[[T1]]
-  ; CMOV-32:    mov.d   $f0, $f14
+  ; CMOV-32:      lw        $[[T0:[0-9]+]], 16($sp)
+  ; CMOV-32:      andi      $[[T1:[0-9]+]], $[[T0]], 1
+  ; CMOV-32:      movn.d    $f14, $f12, $[[T1]]
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     lw      $[[T0:[0-9]+]], 16($sp)
-  ; SEL-32:     mtc1    $[[T0]], $f0
-  ; SEL-32:     sel.d   $f0, $f14, $f12
+  ; SEL-32:       lw        $[[T0:[0-9]+]], 16($sp)
+  ; SEL-32:       mtc1      $[[T0]], $f0
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; M3:         andi    $[[T0:[0-9]+]], $6, 1
-  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M3:         nop
-  ; M3:         mov.d   $f12, $f13
-  ; M3:         $[[BB0]]:
-  ; M3:         jr      $ra
-  ; M3:         mov.d   $f0, $f12
+  ; M3:           andi      $[[T0:[0-9]+]], $6, 1
+  ; M3:           bnez      $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:           nop
+  ; M3:           mov.d     $f12, $f13
+  ; M3:           $[[BB0]]:
+  ; M3:           jr        $ra
+  ; M3:           mov.d     $f0, $f12
 
-  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
-  ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
-  ; CMOV-64:    mov.d   $f0, $f13
+  ; CMOV-64:      andi      $[[T0:[0-9]+]], $6, 1
+  ; CMOV-64:      movn.d    $f13, $f12, $[[T0]]
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     mtc1    $6, $f0
-  ; SEL-64:     sel.d   $f0, $f13, $f12
+  ; SEL-64:       dmtc1     $6, $f0
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_olt_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_olt_double:
 
-  ; M2:         c.olt.d   $f12, $f14
-  ; M3:         c.olt.d   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.d     $f12, $f14
-  ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.d     $f0, $f12
+  ; M2:           c.olt.d   $f12, $f14
+  ; M3:           c.olt.d   $f12, $f13
+  ; M2-M3:        bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.d     $f12, $f14
+  ; M3:           mov.d     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.d     $f0, $f12
 
-  ; CMOV-32:    c.olt.d   $f12, $f14
-  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.d     $f0, $f14
+  ; CMOV-32:      c.olt.d   $f12, $f14
+  ; CMOV-32:      movt.d    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     cmp.lt.d  $f0, $f12, $f14
-  ; SEL-32:     sel.d     $f0, $f14, $f12
+  ; SEL-32:       cmp.lt.d  $f0, $f12, $f14
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; CMOV-64:    c.olt.d   $f12, $f13
-  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.d     $f0, $f13
+  ; CMOV-64:      c.olt.d   $f12, $f13
+  ; CMOV-64:      movt.d    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     cmp.lt.d  $f0, $f12, $f13
-  ; SEL-64:     sel.d     $f0, $f13, $f12
+  ; SEL-64:       cmp.lt.d  $f0, $f12, $f13
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %s = fcmp olt double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_ole_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ole_double:
 
-  ; M2:         c.ole.d   $f12, $f14
-  ; M3:         c.ole.d   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.d     $f12, $f14
-  ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.d     $f0, $f12
+  ; M2:           c.ole.d   $f12, $f14
+  ; M3:           c.ole.d   $f12, $f13
+  ; M2-M3:        bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.d     $f12, $f14
+  ; M3:           mov.d     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.d     $f0, $f12
 
-  ; CMOV-32:    c.ole.d   $f12, $f14
-  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.d     $f0, $f14
+  ; CMOV-32:      c.ole.d   $f12, $f14
+  ; CMOV-32:      movt.d    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     cmp.le.d  $f0, $f12, $f14
-  ; SEL-32:     sel.d     $f0, $f14, $f12
+  ; SEL-32:       cmp.le.d  $f0, $f12, $f14
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ole.d   $f12, $f13
-  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.d     $f0, $f13
+  ; CMOV-64:      c.ole.d   $f12, $f13
+  ; CMOV-64:      movt.d    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     cmp.le.d  $f0, $f12, $f13
-  ; SEL-64:     sel.d     $f0, $f13, $f12
+  ; SEL-64:       cmp.le.d  $f0, $f12, $f13
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %s = fcmp ole double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_ogt_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ogt_double:
 
-  ; M2:         c.ule.d   $f12, $f14
-  ; M3:         c.ule.d   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.d     $f12, $f14
-  ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.d     $f0, $f12
+  ; M2:           c.ule.d   $f12, $f14
+  ; M3:           c.ule.d   $f12, $f13
+  ; M2-M3:        bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.d     $f12, $f14
+  ; M3:           mov.d     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.d     $f0, $f12
 
-  ; CMOV-32:    c.ule.d   $f12, $f14
-  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.d     $f0, $f14
+  ; CMOV-32:      c.ule.d   $f12, $f14
+  ; CMOV-32:      movf.d    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     cmp.lt.d  $f0, $f14, $f12
-  ; SEL-32:     sel.d     $f0, $f14, $f12
+  ; SEL-32:       cmp.lt.d  $f0, $f14, $f12
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ule.d   $f12, $f13
-  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.d     $f0, $f13
+  ; CMOV-64:      c.ule.d   $f12, $f13
+  ; CMOV-64:      movf.d    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     cmp.lt.d  $f0, $f13, $f12
-  ; SEL-64:     sel.d     $f0, $f13, $f12
+  ; SEL-64:       cmp.lt.d  $f0, $f13, $f12
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %s = fcmp ogt double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_oge_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oge_double:
 
-  ; M2:         c.ult.d   $f12, $f14
-  ; M3:         c.ult.d   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.d     $f12, $f14
-  ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.d     $f0, $f12
+  ; M2:           c.ult.d   $f12, $f14
+  ; M3:           c.ult.d   $f12, $f13
+  ; M2-M3:        bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.d     $f12, $f14
+  ; M3:           mov.d     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.d     $f0, $f12
 
-  ; CMOV-32:    c.ult.d   $f12, $f14
-  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.d     $f0, $f14
+  ; CMOV-32:      c.ult.d   $f12, $f14
+  ; CMOV-32:      movf.d    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     cmp.le.d  $f0, $f14, $f12
-  ; SEL-32:     sel.d     $f0, $f14, $f12
+  ; SEL-32:       cmp.le.d  $f0, $f14, $f12
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ult.d   $f12, $f13
-  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.d     $f0, $f13
+  ; CMOV-64:      c.ult.d   $f12, $f13
+  ; CMOV-64:      movf.d    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     cmp.le.d  $f0, $f13, $f12
-  ; SEL-64:     sel.d     $f0, $f13, $f12
+  ; SEL-64:       cmp.le.d  $f0, $f13, $f12
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %s = fcmp oge double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_oeq_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oeq_double:
 
-  ; M2:         c.eq.d    $f12, $f14
-  ; M3:         c.eq.d    $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.d     $f12, $f14
-  ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.d     $f0, $f12
+  ; M2:           c.eq.d    $f12, $f14
+  ; M3:           c.eq.d    $f12, $f13
+  ; M2-M3:        bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.d     $f12, $f14
+  ; M3:           mov.d     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.d     $f0, $f12
 
-  ; CMOV-32:    c.eq.d    $f12, $f14
-  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.d     $f0, $f14
+  ; CMOV-32:      c.eq.d    $f12, $f14
+  ; CMOV-32:      movt.d    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     cmp.eq.d  $f0, $f12, $f14
-  ; SEL-32:     sel.d     $f0, $f14, $f12
+  ; SEL-32:       cmp.eq.d  $f0, $f12, $f14
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; CMOV-64:    c.eq.d    $f12, $f13
-  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.d     $f0, $f13
+  ; CMOV-64:      c.eq.d    $f12, $f13
+  ; CMOV-64:      movt.d    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     cmp.eq.d  $f0, $f12, $f13
-  ; SEL-64:     sel.d     $f0, $f13, $f12
+  ; SEL-64:       cmp.eq.d  $f0, $f12, $f13
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %s = fcmp oeq double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
 define double @tst_select_fcmp_one_double(double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_one_double:
 
-  ; M2:         c.ueq.d   $f12, $f14
-  ; M3:         c.ueq.d   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.d     $f12, $f14
-  ; M3:         mov.d     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.d     $f0, $f12
+  ; M2:           c.ueq.d   $f12, $f14
+  ; M3:           c.ueq.d   $f12, $f13
+  ; M2-M3:        bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.d     $f12, $f14
+  ; M3:           mov.d     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.d     $f0, $f12
 
-  ; CMOV-32:    c.ueq.d   $f12, $f14
-  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.d     $f0, $f14
+  ; CMOV-32:      c.ueq.d   $f12, $f14
+  ; CMOV-32:      movf.d    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.d     $f0, $f14
 
-  ; SEL-32:     cmp.ueq.d $f0, $f12, $f14
-  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
-  ; SEL-32:     not       $[[T0]], $[[T0]]
-  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
-  ; SEL-32:     sel.d     $f0, $f14, $f12
+  ; SEL-32:       cmp.ueq.d $f0, $f12, $f14
+  ; SEL-32:       mfc1      $[[T0:[0-9]+]], $f0
+  ; SEL-32:       not       $[[T0]], $[[T0]]
+  ; SEL-32:       mtc1      $[[T0:[0-9]+]], $f0
+  ; SEL-32:       sel.d     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ueq.d   $f12, $f13
-  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.d     $f0, $f13
+  ; CMOV-64:      c.ueq.d   $f12, $f13
+  ; CMOV-64:      movf.d    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.d     $f0, $f13
 
-  ; SEL-64:     cmp.ueq.d $f0, $f12, $f13
-  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
-  ; SEL-64:     not       $[[T0]], $[[T0]]
-  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
-  ; SEL-64:     sel.d     $f0, $f13, $f12
+  ; SEL-64:       cmp.ueq.d $f0, $f12, $f13
+  ; SEL-64:       mfc1      $[[T0:[0-9]+]], $f0
+  ; SEL-64:       not       $[[T0]], $[[T0]]
+  ; SEL-64:       mtc1      $[[T0:[0-9]+]], $f0
+  ; SEL-64:       sel.d     $f0, $f13, $f12
   %s = fcmp one double %x, %y
   %r = select i1 %s, double %x, double %y
   ret double %r
 }

test/CodeGen/Mips/llvm-ir/select-flt.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV \
 ; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
 define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_float:
 
-  ; M2-M3:      andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         jr      $ra
-  ; M2:         mtc1    $6, $f0
-  ; M3:         mov.s   $f13, $f14
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr      $ra
-  ; M2:         mtc1    $5, $f0
-  ; M3:         mov.s   $f0, $f13
+  ; M2-M3:        andi      $[[T0:[0-9]+]], $4, 1
+  ; M2-M3:        bnez      $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           jr        $ra
+  ; M2:           mtc1      $6, $f0
+  ; M3:           mov.s     $f13, $f14
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2:           mtc1      $5, $f0
+  ; M3:           mov.s     $f0, $f13
 
-  ; CMOV-32:    mtc1    $6, $f0
-  ; CMOV-32:    mtc1    $5, $f1
-  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-32:    movn.s  $f0, $f1, $[[T0]]
+  ; CMOV-32:      mtc1      $6, $f0
+  ; CMOV-32:      mtc1      $5, $f1
+  ; CMOV-32:      andi      $[[T0:[0-9]+]], $4, 1
+  ; CMOV-32:      movn.s    $f0, $f1, $[[T0]]
 
-  ; SEL-32:     mtc1    $5, $[[F0:f[0-9]+]]
-  ; SEL-32:     mtc1    $6, $[[F1:f[0-9]+]]
-  ; SEL-32:     mtc1    $4, $f0
-  ; SEL-32:     sel.s   $f0, $[[F1]], $[[F0]]
+  ; SEL-32:       mtc1      $5, $[[F0:f[0-9]+]]
+  ; SEL-32:       mtc1      $6, $[[F1:f[0-9]+]]
+  ; SEL-32:       mtc1      $4, $f0
+  ; SEL-32:       sel.s     $f0, $[[F1]], $[[F0]]
 
-  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-64:    movn.s  $f14, $f13, $[[T0]]
-  ; CMOV-64:    mov.s   $f0, $f14
+  ; CMOV-64:      andi      $[[T0:[0-9]+]], $4, 1
+  ; CMOV-64:      movn.s    $f14, $f13, $[[T0]]
+  ; CMOV-64:      mov.s     $f0, $f14
 
-  ; SEL-64:     mtc1    $4, $f0
-  ; SEL-64:     sel.s   $f0, $f14, $f13
+  ; SEL-64:       dmtc1     $4, $f0
+  ; SEL-64:       sel.s     $f0, $f14, $f13
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
-define float @tst_select_i1_float_reordered(float %x, float %y,
-                                            i1 signext %s) {
+define float @tst_select_i1_float_reordered(float %x, float %y, i1 signext %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_float_reordered:
 
-  ; M2-M3:      andi    $[[T0:[0-9]+]], $6, 1
-  ; M2-M3:      bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s   $f12, $f14
-  ; M3:         mov.s   $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr      $ra
-  ; M2-M3:      mov.s   $f0, $f12
+  ; M2-M3:        andi      $[[T0:[0-9]+]], $6, 1
+  ; M2-M3:        bnez      $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    andi    $[[T0:[0-9]+]], $6, 1
-  ; CMOV-32:    movn.s  $f14, $f12, $[[T0]]
-  ; CMOV-32:    mov.s   $f0, $f14
+  ; CMOV-32:      andi      $[[T0:[0-9]+]], $6, 1
+  ; CMOV-32:      movn.s    $f14, $f12, $[[T0]]
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     mtc1    $6, $f0
-  ; SEL-32:     sel.s   $f0, $f14, $f12
+  ; SEL-32:       mtc1      $6, $f0
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
-  ; CMOV-64:    movn.s  $f13, $f12, $[[T0]]
-  ; CMOV-64:    mov.s   $f0, $f13
+  ; CMOV-64:      andi      $[[T0:[0-9]+]], $6, 1
+  ; CMOV-64:      movn.s    $f13, $f12, $[[T0]]
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     mtc1    $6, $f0
-  ; SEL-64:     sel.s   $f0, $f13, $f12
+  ; SEL-64:       dmtc1     $6, $f0
+  ; SEL-64:       sel.s     $f0, $f13, $f12
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_olt_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_olt_float:
 
-  ; M2:         c.olt.s   $f12, $f14
-  ; M3:         c.olt.s   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s     $f12, $f14
-  ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.s     $f0, $f12
+  ; M2:           c.olt.s   $f12, $f14
+  ; M3:           c.olt.s   $f12, $f13
+  ; M2-M3:        bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    c.olt.s   $f12, $f14
-  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.s     $f0, $f14
+  ; CMOV-32:      c.olt.s   $f12, $f14
+  ; CMOV-32:      movt.s    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     cmp.lt.s  $f0, $f12, $f14
-  ; SEL-32:     sel.s     $f0, $f14, $f12
+  ; SEL-32:       cmp.lt.s  $f0, $f12, $f14
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    c.olt.s   $f12, $f13
-  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.s     $f0, $f13
+  ; CMOV-64:      c.olt.s   $f12, $f13
+  ; CMOV-64:      movt.s    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     cmp.lt.s  $f0, $f12, $f13
-  ; SEL-64:     sel.s     $f0, $f13, $f12
+  ; SEL-64:       cmp.lt.s  $f0, $f12, $f13
+  ; SEL-64:       sel.s     $f0, $f13, $f12
   %s = fcmp olt float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_ole_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ole_float:
 
-  ; M2:         c.ole.s   $f12, $f14
-  ; M3:         c.ole.s   $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s     $f12, $f14
-  ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.s     $f0, $f12
+  ; M2:           c.ole.s   $f12, $f14
+  ; M3:           c.ole.s   $f12, $f13
+  ; M2-M3:        bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    c.ole.s   $f12, $f14
-  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.s     $f0, $f14
+  ; CMOV-32:      c.ole.s   $f12, $f14
+  ; CMOV-32:      movt.s    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     cmp.le.s  $f0, $f12, $f14
-  ; SEL-32:     sel.s     $f0, $f14, $f12
+  ; SEL-32:       cmp.le.s  $f0, $f12, $f14
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ole.s   $f12, $f13
-  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.s     $f0, $f13
+  ; CMOV-64:      c.ole.s   $f12, $f13
+  ; CMOV-64:      movt.s    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     cmp.le.s  $f0, $f12, $f13
-  ; SEL-64:     sel.s     $f0, $f13, $f12
+  ; SEL-64:       cmp.le.s  $f0, $f12, $f13
+  ; SEL-64:       sel.s     $f0, $f13, $f12
   %s = fcmp ole float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_ogt_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_ogt_float:
 
-  ; M2:         c.ule.s   $f12, $f14
-  ; M3:         c.ule.s   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s     $f12, $f14
-  ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.s     $f0, $f12
+  ; M2:           c.ule.s   $f12, $f14
+  ; M3:           c.ule.s   $f12, $f13
+  ; M2-M3:        bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    c.ule.s   $f12, $f14
-  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.s     $f0, $f14
+  ; CMOV-32:      c.ule.s   $f12, $f14
+  ; CMOV-32:      movf.s    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     cmp.lt.s  $f0, $f14, $f12
-  ; SEL-32:     sel.s     $f0, $f14, $f12
+  ; SEL-32:       cmp.lt.s  $f0, $f14, $f12
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ule.s   $f12, $f13
-  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.s     $f0, $f13
+  ; CMOV-64:      c.ule.s   $f12, $f13
+  ; CMOV-64:      movf.s    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     cmp.lt.s  $f0, $f13, $f12
-  ; SEL-64:     sel.s     $f0, $f13, $f12
+  ; SEL-64:       cmp.lt.s  $f0, $f13, $f12
+  ; SEL-64:       sel.s     $f0, $f13, $f12
   %s = fcmp ogt float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_oge_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oge_float:
 
-  ; M2:         c.ult.s   $f12, $f14
-  ; M3:         c.ult.s   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s     $f12, $f14
-  ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.s     $f0, $f12
+  ; M2:           c.ult.s   $f12, $f14
+  ; M3:           c.ult.s   $f12, $f13
+  ; M2-M3:        bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    c.ult.s   $f12, $f14
-  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.s     $f0, $f14
+  ; CMOV-32:      c.ult.s   $f12, $f14
+  ; CMOV-32:      movf.s    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     cmp.le.s  $f0, $f14, $f12
-  ; SEL-32:     sel.s     $f0, $f14, $f12
+  ; SEL-32:       cmp.le.s  $f0, $f14, $f12
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ult.s   $f12, $f13
-  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.s     $f0, $f13
+  ; CMOV-64:      c.ult.s   $f12, $f13
+  ; CMOV-64:      movf.s    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     cmp.le.s  $f0, $f13, $f12
-  ; SEL-64:     sel.s     $f0, $f13, $f12
+  ; SEL-64:       cmp.le.s  $f0, $f13, $f12
+  ; SEL-64:       sel.s     $f0, $f13, $f12
   %s = fcmp oge float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_oeq_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_oeq_float:
 
-  ; M2:         c.eq.s    $f12, $f14
-  ; M3:         c.eq.s    $f12, $f13
-  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s     $f12, $f14
-  ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.s     $f0, $f12
+  ; M2:           c.eq.s    $f12, $f14
+  ; M3:           c.eq.s    $f12, $f13
+  ; M2-M3:        bc1t      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    c.eq.s    $f12, $f14
-  ; CMOV-32:    movt.s    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.s     $f0, $f14
+  ; CMOV-32:      c.eq.s    $f12, $f14
+  ; CMOV-32:      movt.s    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     cmp.eq.s  $f0, $f12, $f14
-  ; SEL-32:     sel.s     $f0, $f14, $f12
+  ; SEL-32:       cmp.eq.s  $f0, $f12, $f14
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    c.eq.s    $f12, $f13
-  ; CMOV-64:    movt.s    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.s     $f0, $f13
+  ; CMOV-64:      c.eq.s    $f12, $f13
+  ; CMOV-64:      movt.s    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     cmp.eq.s  $f0, $f12, $f13
-  ; SEL-64:     sel.s     $f0, $f13, $f12
+  ; SEL-64:       cmp.eq.s  $f0, $f12, $f13
+  ; SEL-64:       sel.s     $f0, $f13, $f12
   %s = fcmp oeq float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
 define float @tst_select_fcmp_one_float(float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_fcmp_one_float:
 
-  ; M2:         c.ueq.s   $f12, $f14
-  ; M3:         c.ueq.s   $f12, $f13
-  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
-  ; M2-M3:      nop
-  ; M2:         mov.s     $f12, $f14
-  ; M3:         mov.s     $f12, $f13
-  ; M2-M3:      $[[BB0]]:
-  ; M2-M3:      jr        $ra
-  ; M2-M3:      mov.s     $f0, $f12
+  ; M2:           c.ueq.s   $f12, $f14
+  ; M3:           c.ueq.s   $f12, $f13
+  ; M2-M3:        bc1f      $[[BB0:BB[0-9_]+]]
+  ; M2-M3:        nop
+  ; M2:           mov.s     $f12, $f14
+  ; M3:           mov.s     $f12, $f13
+  ; M2-M3:        $[[BB0]]:
+  ; M2-M3:        jr        $ra
+  ; M2-M3:        mov.s     $f0, $f12
 
-  ; CMOV-32:    c.ueq.s   $f12, $f14
-  ; CMOV-32:    movf.s    $f14, $f12, $fcc0
-  ; CMOV-32:    mov.s     $f0, $f14
+  ; CMOV-32:      c.ueq.s   $f12, $f14
+  ; CMOV-32:      movf.s    $f14, $f12, $fcc0
+  ; CMOV-32:      mov.s     $f0, $f14
 
-  ; SEL-32:     cmp.ueq.s $f0, $f12, $f14
-  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
-  ; SEL-32:     not       $[[T0]], $[[T0]]
-  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
-  ; SEL-32:     sel.s     $f0, $f14, $f12
+  ; SEL-32:       cmp.ueq.s $f0, $f12, $f14
+  ; SEL-32:       mfc1      $[[T0:[0-9]+]], $f0
+  ; SEL-32:       not       $[[T0]], $[[T0]]
+  ; SEL-32:       mtc1      $[[T0:[0-9]+]], $f0
+  ; SEL-32:       sel.s     $f0, $f14, $f12
 
-  ; CMOV-64:    c.ueq.s   $f12, $f13
-  ; CMOV-64:    movf.s    $f13, $f12, $fcc0
-  ; CMOV-64:    mov.s     $f0, $f13
+  ; CMOV-64:      c.ueq.s   $f12, $f13
+  ; CMOV-64:      movf.s    $f13, $f12, $fcc0
+  ; CMOV-64:      mov.s     $f0, $f13
 
-  ; SEL-64:     cmp.ueq.s $f0, $f12, $f13
-  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
-  ; SEL-64:     not       $[[T0]], $[[T0]]
-  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
-  ; SEL-64:     sel.s     $f0, $f13, $f12
+  ; SEL-64:       cmp.ueq.s $f0, $f12, $f13
+  ; SEL-64:       mfc1      $[[T0:[0-9]+]], $f0
+  ; SEL-64:       not       $[[T0]], $[[T0]]
+  ; SEL-64:       mtc1      $[[T0:[0-9]+]], $f0
+  ; SEL-64:       sel.s     $f0, $f13, $f12
 
   %s = fcmp one float %x, %y
   %r = select i1 %s, float %x, float %y
   ret float %r
 }

test/CodeGen/Mips/llvm-ir/select-int.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
+; RUN:    -check-prefix=M2
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV \
-; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
+; RUN:    -check-prefix=M32R1
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV \
-; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN:    -check-prefix=M32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV \
-; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN:    -check-prefix=M32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV \
-; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN:    -check-prefix=M32R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+; RUN:    -check-prefix=M32R6
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
+; RUN:    -check-prefix=M3
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN:    -check-prefix=M4
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN:    -check-prefix=M64R1
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN:    -check-prefix=M64R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN:    -check-prefix=M64R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN:    -check-prefix=M64R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN:    -check-prefix=M64R6
 
 define signext i1 @tst_select_i1_i1(i1 signext %s,
                                     i1 signext %x, i1 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i1:
 
-  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2-M3:  nop
-  ; M2-M3:  move    $5, $6
-  ; M2-M3:  $[[BB0]]:
-  ; M2-M3:  jr      $ra
-  ; M2-M3:  move    $2, $5
-
-  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV:   movn    $6, $5, $[[T0]]
-  ; CMOV:   move    $2, $6
-
-  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
-  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
-  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
-  ; SEL:    or      $2, $[[T2]], $[[T1]]
+  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:         nop
+  ; M2:         move    $5, $6
+  ; M2:         $[[BB0]]:
+  ; M2:         jr      $ra
+  ; M2:         move    $2, $5
+
+  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         nop
+  ; M3:         move    $5, $6
+  ; M3:         $[[BB0]]:
+  ; M3:         dsll    $[[T1:[0-9]+]], $5, 63
+  ; M3:         jr      $ra
+  ; M3:         dsra    $2, $[[T1]], 63
+
+  ; M4:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M4:         movn    $6, $5, $[[T0]]
+  ; M4:         dsll    $[[T1:[0-9]+]], $6, 63
+  ; M4:         dsra    $2, $[[T1]], 63
+
+  ; M32R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1:      movn    $6, $5, $[[T0]]
+  ; M32R1:      move    $2, $6
+
+  ; M32R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1-R5:   movn    $6, $5, $[[T0]]
+  ; M32R1-R5:   move    $2, $6
+
+  ; M64R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R1:      movn    $6, $5, $[[T0]]
+  ; M64R1:      dsll    $[[T1:[0-9]+]], $6, 63
+  ; M64R1:      dsra    $2, $[[T1]], 63
+
+  ; M64R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R2-R5:   movn    $6, $5, $[[T0]]
+  ; M64R2-R5:   dsll    $[[T1:[0-9]+]], $6, 63
+  ; M64R2-R5:   dsra    $2, $[[T1]], 63
+
+  ; M32R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M32R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M32R6:      or      $2, $[[T2]], $[[T1]]
+
+  ; M64R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M64R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M64R6:      or      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M64R6:      dsll    $[[T4:[0-9]+]], $[[T3]], 63
+  ; M64R6:      dsra    $2, $[[T4]], 63
+
   %r = select i1 %s, i1 %x, i1 %y
   ret i1 %r
 }
 
 define signext i8 @tst_select_i1_i8(i1 signext %s,
                                     i8 signext %x, i8 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i8:
 
-  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2-M3:  nop
-  ; M2-M3:  move    $5, $6
-  ; M2-M3:  $[[BB0]]:
-  ; M2-M3:  jr      $ra
-  ; M2-M3:  move    $2, $5
-
-  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV:   movn    $6, $5, $[[T0]]
-  ; CMOV:   move    $2, $6
-
-  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
-  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
-  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
-  ; SEL:    or      $2, $[[T2]], $[[T1]]
+  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:         nop
+  ; M2:         move    $5, $6
+  ; M2:         $[[BB0]]:
+  ; M2:         jr      $ra
+  ; M2:         move    $2, $5
+
+  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         nop
+  ; M3:         move    $5, $6
+  ; M3:         $[[BB0]]:
+  ; M3:         dsll    $[[T1:[0-9]+]], $5, 56
+  ; M3:         jr      $ra
+  ; M3:         dsra    $2, $[[T1]], 56
+
+  ; M4:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M4:         movn    $6, $5, $[[T0]]
+  ; M4:         dsll    $[[T1:[0-9]+]], $6, 56
+  ; M4:         dsra    $2, $[[T1]], 56
+
+  ; M32R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1:      movn    $6, $5, $[[T0]]
+  ; M32R1:      move    $2, $6
+
+  ; M32R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1-R5:   movn    $6, $5, $[[T0]]
+  ; M32R1-R5:   move    $2, $6
+
+  ; M64R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R1:      movn    $6, $5, $[[T0]]
+  ; M64R1:      dsll    $[[T1:[0-9]+]], $6, 56
+  ; M64R1:      dsra    $2, $[[T1]], 56
+
+  ; M64R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R2-R5:   movn    $6, $5, $[[T0]]
+  ; M64R2-R5:   seb     $2, $6
+
+  ; M32R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M32R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M32R6:      or      $2, $[[T2]], $[[T1]]
+
+  ; M64R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M64R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M64R6:      or      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M64R6:      seb     $2, $[[T3]]
+
   %r = select i1 %s, i8 %x, i8 %y
   ret i8 %r
 }
 
+define signext i16 @tst_select_i1_i16(i1 signext %s,
+                                    i16 signext %x, i16 signext %y) {
+entry:
+  ; ALL-LABEL: tst_select_i1_i16:
+
+  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:         nop
+  ; M2:         move    $5, $6
+  ; M2:         $[[BB0]]:
+  ; M2:         jr      $ra
+  ; M2:         move    $2, $5
+
+  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         nop
+  ; M3:         move    $5, $6
+  ; M3:         $[[BB0]]:
+  ; M3:         dsll    $[[T1:[0-9]+]], $5, 48
+  ; M3:         jr      $ra
+  ; M3:         dsra    $2, $[[T1]], 48
+
+  ; M4:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M4:         movn    $6, $5, $[[T0]]
+  ; M4:         dsll    $[[T1:[0-9]+]], $6, 48
+  ; M4:         dsra    $2, $[[T1]], 48
+
+  ; M32R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1:      movn    $6, $5, $[[T0]]
+  ; M32R1:      move    $2, $6
+
+  ; M32R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1-R5:   movn    $6, $5, $[[T0]]
+  ; M32R1-R5:   move    $2, $6
+
+  ; M64R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R1:      movn    $6, $5, $[[T0]]
+  ; M64R1:      dsll    $[[T1:[0-9]+]], $6, 48
+  ; M64R1:      dsra    $2, $[[T1]], 48
+
+  ; M64R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R2-R5:   movn    $6, $5, $[[T0]]
+  ; M64R2-R5:   seh     $2, $6
+
+  ; M32R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M32R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M32R6:      or      $2, $[[T2]], $[[T1]]
+
+  ; M64R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M64R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M64R6:      or      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M64R6:      seh     $2, $[[T3]]
+
+  %r = select i1 %s, i16 %x, i16 %y
+  ret i16 %r
+}
+
 define signext i32 @tst_select_i1_i32(i1 signext %s,
                                       i32 signext %x, i32 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i32:
 
-  ; M2-M3:  andi    $[[T0:[0-9]+]], $4, 1
-  ; M2-M3:  bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2-M3:  nop
-  ; M2-M3:  move    $5, $6
-  ; M2-M3:  $[[BB0]]:
-  ; M2-M3:  jr      $ra
-  ; M2-M3:  move    $2, $5
-
-  ; CMOV:   andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV:   movn    $6, $5, $[[T0]]
-  ; CMOV:   move    $2, $6
-
-  ; SEL:    andi    $[[T0:[0-9]+]], $4, 1
-  ; SEL:    seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
-  ; SEL:    selnez  $[[T2:[0-9]+]], $5, $[[T0]]
-  ; SEL:    or      $2, $[[T2]], $[[T1]]
+  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:         nop
+  ; M2:         move    $5, $6
+  ; M2:         $[[BB0]]:
+  ; M2:         jr      $ra
+  ; M2:         move    $2, $5
+
+  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M3:         nop
+  ; M3:         move    $5, $6
+  ; M3:         $[[BB0]]:
+  ; M3:         jr      $ra
+  ; M3:         sll     $2, $5, 0
+
+  ; M4:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M4:         movn    $6, $5, $[[T0]]
+  ; M4:         sll     $2, $6, 0
+
+  ; M32R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1:      movn    $6, $5, $[[T0]]
+  ; M32R1:      move    $2, $6
+
+  ; M32R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R2-R5:   movn    $6, $5, $[[T0]]
+  ; M32R2-R5:   move    $2, $6
+
+  ; M64R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R1:      movn    $6, $5, $[[T0]]
+
+  ; M64R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R2-R5:   movn    $6, $5, $[[T0]]
+  ; M64R2-R5:   sll     $2, $6, 0
+
+  ; M32R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M32R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M32R6:      or      $2, $[[T2]], $[[T1]]
+
+  ; M64R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M64R6:      selnez  $[[T2:[0-9]+]], $5, $[[T0]]
+  ; M64R6:      or      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M64R6:      sll     $2, $[[T3]], 0
+
   %r = select i1 %s, i32 %x, i32 %y
   ret i32 %r
 }
 
 define signext i64 @tst_select_i1_i64(i1 signext %s,
                                       i64 signext %x, i64 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i64:
 
-  ; M2:     andi    $[[T0:[0-9]+]], $4, 1
-  ; M2:     bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
-  ; M2:     nop
-  ; M2:     lw      $[[T1:[0-9]+]], 16($sp)
-  ; M2:     $[[BB0]]:
+  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
+  ; M2:         nop
+  ; M2:         lw      $[[T1:[0-9]+]], 16($sp)
+  ; M2:         $[[BB0]]:
   ; FIXME: This branch is redundant
-  ; M2:     bnez    $[[T0]], $[[BB1:BB[0-9_]+]]
-  ; M2:     nop
-  ; M2:     lw      $[[T2:[0-9]+]], 20($sp)
-  ; M2:     $[[BB1]]:
-  ; M2:     move    $2, $[[T1]]
-  ; M2:     jr      $ra
-  ; M2:     move    $3, $[[T2]]
+  ; M2:         bnez    $[[T0]], $[[BB1:BB[0-9_]+]]
+  ; M2:         nop
+  ; M2:         lw      $[[T2:[0-9]+]], 20($sp)
+  ; M2:         $[[BB1]]:
+  ; M2:         move    $2, $[[T1]]
+  ; M2:         jr      $ra
+  ; M2:         move    $3, $[[T2]]
 
-  ; CMOV-32:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-32:    lw      $2, 16($sp)
-  ; CMOV-32:    movn    $2, $6, $[[T0]]
-  ; CMOV-32:    lw      $3, 20($sp)
-  ; CMOV-32:    movn    $3, $7, $[[T0]]
-
-  ; SEL-32:     andi    $[[T0:[0-9]+]], $4, 1
-  ; SEL-32:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
-  ; SEL-32:     lw      $[[T2:[0-9]+]], 16($sp)
-  ; SEL-32:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
-  ; SEL-32:     or      $2, $[[T1]], $[[T3]]
-  ; SEL-32:     selnez  $[[T4:[0-9]+]], $7, $[[T0]]
-  ; SEL-32:     lw      $[[T5:[0-9]+]], 20($sp)
-  ; SEL-32:     seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
-  ; SEL-32:     or      $3, $[[T4]], $[[T6]]
-
   ; M3:         andi    $[[T0:[0-9]+]], $4, 1
   ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
   ; M3:         nop
   ; M3:         move    $5, $6
   ; M3:         $[[BB0]]:
   ; M3:         jr      $ra
   ; M3:         move    $2, $5
 
-  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
-  ; CMOV-64:    movn    $6, $5, $[[T0]]
-  ; CMOV-64:    move    $2, $6
-
-  ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
-  ; FIXME: This shift is redundant
-  ; SEL-64:     sll     $[[T0]], $[[T0]], 0
-  ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
-  ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
-  ; SEL-64:     or      $2, $[[T0]], $[[T1]]
+  ; M4:         andi    $[[T0:[0-9]+]], $4, 1
+  ; M4:         movn    $6, $5, $[[T0]]
+  ; M4:         move    $2, $6
+
+  ; M32R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R1:      lw      $2, 16($sp)
+  ; M32R1:      movn    $2, $6, $[[T0]]
+  ; M32R1:      lw      $3, 20($sp)
+  ; M32R1:      movn    $3, $7, $[[T0]]
+
+  ; M32R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R2-R5:   lw      $2, 16($sp)
+  ; M32R2-R5:   movn    $2, $6, $[[T0]]
+  ; M32R2-R5:   lw      $3, 20($sp)
+  ; M32R2-R5:   movn    $3, $7, $[[T0]]
+
+  ; M32R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M32R6:      selnez  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M32R6:      lw      $[[T2:[0-9]+]], 16($sp)
+  ; M32R6:      seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
+  ; M32R6:      or      $2, $[[T1]], $[[T3]]
+  ; M32R6:      selnez  $[[T4:[0-9]+]], $7, $[[T0]]
+  ; M32R6:      lw      $[[T5:[0-9]+]], 20($sp)
+  ; M32R6:      seleqz  $[[T6:[0-9]+]], $[[T5]], $[[T0]]
+  ; M32R6:      or      $3, $[[T4]], $[[T6]]
+
+  ; M64R1:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R1:      movn    $6, $5, $[[T0]]
+  ; M64R1:      move    $2, $6
+
+  ; M64R2-R5:   andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R2-R5:   movn    $6, $5, $[[T0]]
+  ; M64R2-R5:   move    $2, $6
+
+  ; M64R6:      andi    $[[T0:[0-9]+]], $4, 1
+  ; M64R6:      seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; M64R6:      selnez  $[[T0]], $5, $[[T0]]
+  ; M64R6:      or      $2, $[[T0]], $[[T1]]
   %r = select i1 %s, i64 %x, i64 %y
   ret i64 %r
 }

test/CodeGen/Mips/llvm-ir/shl.ll

-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=M2 -check-prefix=NOT-R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN:    -check-prefix=32R1-R5
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R1-R5 -check-prefix=R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP32 \
-; RUN:    -check-prefix=32R6 -check-prefix=R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=M3 -check-prefix=NOT-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=GP64 \
-; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M2 -check-prefix=GP32-NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M32R1-R5 -check-prefix=GP32-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP32-R2-R6
+
+; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=M3 -check-prefix=GP64-NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-NOT-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=GP64-R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
+; RUN:    -check-prefix=GP64-R2-R6
 
 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: shl_i1:
 
-  ; ALL:        move    $2, $4
+  ; ALL:            move      $2, $4
 
   %r = shl i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @shl_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: shl_i8:
 
-  ; NOT-R2-R6:  andi    $[[T0:[0-9]+]], $5, 255
-  ; NOT-R2-R6:  sllv    $[[T1:[0-9]+]], $4, $[[T0]]
-  ; NOT-R2-R6:  sll     $[[T2:[0-9]+]], $[[T1]], 24
-  ; NOT-R2-R6:  sra     $2, $[[T2]], 24
-
-  ; R2-R6:      andi    $[[T0:[0-9]+]], $5, 255
-  ; R2-R6:      sllv    $[[T1:[0-9]+]], $4, $[[T0]]
-  ; R2-R6:      seb     $2, $[[T1]]
+  ; GP32-NOT-R2-R6:          andi      $[[T0:[0-9]+]], $5, 255
+  ; GP32-NOT-R2-R6:          sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP32-NOT-R2-R6:          sll       $[[T2:[0-9]+]], $[[T1]], 24
+  ; GP32-NOT-R2-R6:          sra       $2, $[[T2]], 24
+
+  ; GP32-R2-R6:              andi      $[[T0:[0-9]+]], $5, 255
+  ; GP32-R2-R6:              sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP32-R2-R6:              seb       $2, $[[T1]]
+
+  ; M32R6:                   andi      $[[T0:[0-9]+]], $5, 255
+  ; M32R6:                   sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; M32R6:                   seb       $2, $[[T1]]
+
+  ; GP64-NOT-R2-R6:          andi      $[[T0:[0-9]+]], $5, 255
+  ; GP64-NOT-R2-R6:          sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-NOT-R2-R6:          dsll      $[[T2:[0-9]+]], $[[T1]], 56
+  ; GP64-NOT-R2-R6:          dsra      $2, $[[T2]], 56
+
+  ; GP64-R2-R6:              andi      $[[T0:[0-9]+]], $5, 255
+  ; GP64-R2-R6:              sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-R2-R6:              seb       $2, $[[T1]]
 
   %r = shl i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @shl_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: shl_i16:
 
-  ; NOT-R2-R6:  andi    $[[T0:[0-9]+]], $5, 65535
-  ; NOT-R2-R6:  sllv    $[[T1:[0-9]+]], $4, $[[T0]]
-  ; NOT-R2-R6:  sll     $[[T2:[0-9]+]], $[[T1]], 16
-  ; NOT-R2-R6:  sra     $2, $[[T2]], 16
-
-  ; R2-R6:      andi    $[[T0:[0-9]+]], $5, 65535
-  ; R2-R6:      sllv    $[[T1:[0-9]+]], $4, $[[T0]]
-  ; R2-R6:      seh     $2, $[[T1]]
+  ; GP32-NOT-R2-R6: andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP32-NOT-R2-R6: sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP32-NOT-R2-R6: sll       $[[T2:[0-9]+]], $[[T1]], 16
+  ; GP32-NOT-R2-R6: sra       $2, $[[T2]], 16
+
+  ; GP32-R2-R6:     andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP32-R2-R6:     sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP32-R2-R6:     seh       $2, $[[T1]]
+
+  ; M32R6:          andi      $[[T0:[0-9]+]], $5, 65535
+  ; M32R6:          sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; M32R6:          seh       $2, $[[T1]]
+
+  ; GP64-NOT-R2-R6: andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP64-NOT-R2-R6: sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-NOT-R2-R6: dsll      $[[T2:[0-9]+]], $[[T1]], 48
+  ; GP64-NOT-R2-R6: dsra      $2, $[[T2]], 48
+
+  ; GP64-R2-R6:     andi      $[[T0:[0-9]+]], $5, 65535
+  ; GP64-R2-R6:     sllv      $[[T1:[0-9]+]], $4, $[[T0]]
+  ; GP64-R2-R6:     seh       $2, $[[T1]]
 
   %r = shl i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @shl_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: shl_i32:
 
-  ; ALL:        sllv    $2, $4, $5
+  ; GP32-NOT-R2-R6: sllv      $2, $4, $5
+
+  ; GP32-R2-R6:     sllv      $2, $4, $5
+
+  ; GP64-NOT-R2-R6: sllv      $[[T0:[0-9]+]], $4, $5
+  ; GP64-NOT-R2-R6: sll       $2, $[[T0]], 0
+
+  ; GP64-R2-R6:     sllv      $[[T0:[0-9]+]], $4, $5
+  ; GP64-R2-R6:     sll       $2, $[[T0]], 0
 
   %r = shl i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: shl_i64:
; ALL-LABEL: shl_i64:
   ; M2:         $[[BB0]]:
   ; M2:         bnez      $[[T1]], $[[BB1:BB[0-9_]+]]
   ; M2:         addiu     $3, $zero, 0
   ; M2:         move      $3, $[[T0]]
   ; M2:         $[[BB1]]:
   ; M2:         jr        $ra
   ; M2:         nop
 
-  ; 32R1-R5:    sllv      $[[T0:[0-9]+]], $4, $7
-  ; 32R1-R5:    not       $[[T1:[0-9]+]], $7
-  ; 32R1-R5:    srl       $[[T2:[0-9]+]], $5, 1
-  ; 32R1-R5:    srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R1-R5:    or        $2, $[[T0]], $[[T3]]
-  ; 32R1-R5:    sllv      $[[T4:[0-9]+]], $5, $7
-  ; 32R1-R5:    andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R1-R5:    movn      $2, $[[T4]], $[[T5]]
-  ; 32R1-R5:    jr        $ra
-  ; 32R1-R5:    movn      $3, $zero, $[[T5]]
-
-  ; 32R6:       sllv      $[[T0:[0-9]+]], $4, $7
-  ; 32R6:       not       $[[T1:[0-9]+]], $7
-  ; 32R6:       srl       $[[T2:[0-9]+]], $5, 1
-  ; 32R6:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; 32R6:       or        $[[T4:[0-9]+]], $[[T0]], $[[T3]]
-  ; 32R6:       andi      $[[T5:[0-9]+]], $7, 32
-  ; 32R6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T2]]
-  ; 32R6:       sllv      $[[T7:[0-9]+]], $5, $7
-  ; 32R6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
-  ; 32R6:       or        $2, $[[T8]], $[[T6]]
-  ; 32R6:       jr        $ra
-  ; 32R6:       seleqz    $3, $[[T7]], $[[T5]]
+  ; M32R1-R5:   sllv      $[[T0:[0-9]+]], $4, $7
+  ; M32R1-R5:   not       $[[T1:[0-9]+]], $7
+  ; M32R1-R5:   srl       $[[T2:[0-9]+]], $5, 1
+  ; M32R1-R5:   srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M32R1-R5:   or        $2, $[[T0]], $[[T3]]
+  ; M32R1-R5:   sllv      $[[T4:[0-9]+]], $5, $7
+  ; M32R1-R5:   andi      $[[T5:[0-9]+]], $7, 32
+  ; M32R1-R5:   movn      $2, $[[T4]], $[[T5]]
+  ; M32R1-R5:   jr        $ra
+  ; M32R1-R5:   movn      $3, $zero, $[[T5]]
+
+  ; M32R6:      sllv      $[[T0:[0-9]+]], $4, $7
+  ; M32R6:      not       $[[T1:[0-9]+]], $7
+  ; M32R6:      srl       $[[T2:[0-9]+]], $5, 1
+  ; M32R6:      srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; M32R6:      or        $[[T4:[0-9]+]], $[[T0]], $[[T3]]
+  ; M32R6:      andi      $[[T5:[0-9]+]], $7, 32
+  ; M32R6:      seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T2]]
+  ; M32R6:      sllv      $[[T7:[0-9]+]], $5, $7
+  ; M32R6:      selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+  ; M32R6:      or        $2, $[[T8]], $[[T6]]
+  ; M32R6:      jr        $ra
+  ; M32R6:      seleqz    $3, $[[T7]], $[[T5]]
 
-  ; GP64:       dsllv     $2, $4, $5
+  ; GP64-NOT-R2-R6:  dsllv     $2, $4, $5
 
   %r = shl i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: shl_i128:
; ALL-LABEL: shl_i128:
   ; GP64-NOT-R6:    dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
   ; GP64-NOT-R6:    or        $2, $[[T0]], $[[T4]]
   ; GP64-NOT-R6:    dsllv     $3, $5, $7
   ; GP64-NOT-R6:    andi      $[[T5:[0-9]+]], $[[T2]], 64
   ; GP64-NOT-R6:    movn      $2, $3, $[[T5]]
   ; GP64-NOT-R6:    jr        $ra
   ; GP64-NOT-R6:    movn      $3, $zero, $1
 
-  ; 64R6:           dsllv     $[[T0:[0-9]+]], $4, $7
-  ; 64R6:           dsrl      $[[T1:[0-9]+]], $5, 1
-  ; 64R6:           sll       $[[T2:[0-9]+]], $7, 0
-  ; 64R6:           not       $[[T3:[0-9]+]], $[[T2]]
-  ; 64R6:           dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
-  ; 64R6:           or        $[[T5:[0-9]+]], $[[T0]], $[[T4]]
-  ; 64R6:           andi      $[[T6:[0-9]+]], $[[T2]], 64
-  ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
-  ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
-  ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $7
-  ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
-  ; 64R6:           or        $2, $[[T10]], $[[T8]]
-  ; 64R6:           jr        $ra
-  ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
+  ; M64R6:          dsllv     $[[T0:[0-9]+]], $4, $7
+  ; M64R6:          dsrl      $[[T1:[0-9]+]], $5, 1
+  ; M64R6:          sll       $[[T2:[0-9]+]], $7, 0
+  ; M64R6:          not       $[[T3:[0-9]+]], $[[T2]]
+  ; M64R6:          dsrlv     $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+  ; M64R6:          or        $[[T5:[0-9]+]], $[[T0]], $[[T4]]
+  ; M64R6:          andi      $[[T6:[0-9]+]], $[[T2]], 64
+  ; M64R6:          sll       $[[T7:[0-9]+]], $[[T6]], 0
+  ; M64R6:          seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
+  ; M64R6:          dsllv     $[[T9:[0-9]+]], $5, $7
+  ; M64R6:          selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
+  ; M64R6:          or        $2, $[[T10]], $[[T8]]
+  ; M64R6:          jr        $ra
+  ; M64R6:          seleqz    $3, $[[T9]], $[[T7]]
 
   %r = shl i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/srem.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=GP32-NOT-R2-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=GP32-NOT-R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=GP32-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=GP32-R6 -check-prefix=R6
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix=R2-R5
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=GP64-R6 -check-prefix=R6
 
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: srem_i1:
 
-  ; NOT-R6:       div     $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mfhi    $[[T0:[0-9]+]]
-  ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
-  ; NOT-R6:       sra     $2, $[[T1]], 31
+  ; GP32-NOT-R6:      div     $zero, $4, $5
+  ; GP32-NOT-R6:      teq     $5, $zero, 7
+  ; GP32-NOT-R6:      mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP32-NOT-R6:      sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; GP32-NOT-R6:      sra     $2, $[[T1]], 31
 
-  ; R6:           mod     $[[T0:[0-9]+]], $4, $5
-  ; R6:           teq     $5, $zero, 7
-  ; R6:           sll     $[[T3:[0-9]+]], $[[T0]], 31
-  ; R6:           sra     $2, $[[T3]], 31
+  ; GP64-NOT-R6:      div     $zero, $4, $5
+  ; GP64-NOT-R6:      teq     $5, $zero, 7
+  ; GP64-NOT-R6:      mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The dsll/dsra instructions are redundant since div is signed.
+  ; GP64-NOT-R6:      dsll     $[[T1:[0-9]+]], $[[T0]], 63
+  ; GP64-NOT-R6:      dsra     $2, $[[T1]], 63
+
+  ; GP32-R6:          mod     $[[T0:[0-9]+]], $4, $5
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP32-R6:          sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; GP32-R6:          sra     $2, $[[T1]], 31
+
+  ; GP64-R6:          mod     $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP64-R6:          dsll    $[[T1:[0-9]+]], $[[T0]], 63
+  ; GP64-R6:          dsra    $2, $[[T1]], 63
 
   %r = srem i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: srem_i8:
 
-  ; NOT-R2-R6:    div     $zero, $4, $5
-  ; NOT-R2-R6:    teq     $5, $zero, 7
-  ; NOT-R2-R6:    mfhi    $[[T0:[0-9]+]]
-  ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 24
-  ; NOT-R2-R6:    sra     $2, $[[T1]], 24
+  ; GP32-NOT-R2-R6:   div     $zero, $4, $5
+  ; GP32-NOT-R2-R6:   teq     $5, $zero, 7
+  ; GP32-NOT-R2-R6:   mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP32-NOT-R2-R6:   sll     $[[T1:[0-9]+]], $[[T0]], 24
+  ; GP32-NOT-R2-R6:   sra     $2, $[[T1]], 24
 
-  ; R2-R5:        div     $zero, $4, $5
-  ; R2-R5:        teq     $5, $zero, 7
-  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
-  ; R2-R5:        seb     $2, $[[T0]]
+  ; R2-R5:            div     $zero, $4, $5
+  ; R2-R5:            teq     $5, $zero, 7
+  ; R2-R5:            mfhi    $[[T0:[0-9]+]]
+  ; FIXME: This instruction is redundant.
+  ; R2-R5:            seb     $2, $[[T0]]
 
-  ; R6:           mod     $[[T0:[0-9]+]], $4, $5
-  ; R6:           teq     $5, $zero, 7
-  ; R6:           seb     $2, $[[T0]]
+  ; R6:               mod     $[[T0:[0-9]+]], $4, $5
+  ; R6:               teq     $5, $zero, 7
+  ; FIXME: This instruction is redundant.
+  ; R6:               seb     $2, $[[T0]]
 
   %r = srem i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: srem_i16:
 
-  ; NOT-R2-R6:    div     $zero, $4, $5
-  ; NOT-R2-R6:    teq     $5, $zero, 7
-  ; NOT-R2-R6:    mfhi    $[[T0:[0-9]+]]
-  ; NOT-R2-R6:    sll     $[[T1:[0-9]+]], $[[T0]], 16
-  ; NOT-R2-R6:    sra     $2, $[[T1]], 16
+  ; GP32-NOT-R2-R6:   div     $zero, $4, $5
+  ; GP32-NOT-R2-R6:   teq     $5, $zero, 7
+  ; GP32-NOT-R2-R6:   mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP32-NOT-R2-R6:   sll     $[[T1:[0-9]+]], $[[T0]], 16
+  ; GP32-NOT-R2-R6:   sra     $2, $[[T1]], 16
 
-  ; R2-R5:        div     $zero, $4, $5
-  ; R2-R5:        teq     $5, $zero, 7
-  ; R2-R5:        mfhi    $[[T0:[0-9]+]]
-  ; R2-R5:        seh     $2, $[[T1]]
+  ; R2-R5:            div     $zero, $4, $5
+  ; R2-R5:            teq     $5, $zero, 7
+  ; R2-R5:            mfhi    $[[T0:[0-9]+]]
+  ; FIXME: This instruction is redundant.
+  ; R2-R5:            seh     $2, $[[T0]]
 
-  ; R6:           mod     $[[T0:[0-9]+]], $4, $5
-  ; R6:           teq     $5, $zero, 7
-  ; R6:           seh     $2, $[[T0]]
+  ; R6:               mod     $[[T0:[0-9]+]], $4, $5
+  ; R6:               teq     $5, $zero, 7
+  ; FIXME: This instruction is redundant.
+  ; R6:               seh     $2, $[[T0]]
 
   %r = srem i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: srem_i32:
 
-  ; NOT-R6:       div     $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mfhi    $2
+  ; GP32-NOT-R6:      div     $zero, $4, $5
+  ; GP32-NOT-R6:      teq     $5, $zero, 7
+  ; GP32-NOT-R6:      mfhi    $2
 
-  ; R6:           mod     $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP64-NOT-R6:      div     $zero, $4, $5
+  ; GP64-NOT-R6:      teq     $5, $zero, 7
+  ; GP64-NOT-R6:      mfhi    $[[T0:[0-9]+]]
+  ; GP64-NOT-R6:      sll     $2, $[[T0]], 0
+
+  ; GP32-R6:          mod     $2, $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+
+  ; GP64-R6:          mod     $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; GP64-R6:          sll     $2, $[[T0]], 0
 
   %r = srem i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: srem_i64:
 
-  ; GP32:         lw      $25, %call16(__moddi3)($gp)
+  ; GP32-NOT-R6:      lw      $25, %call16(__moddi3)($gp)
+  ; GP32-R6:          lw      $25, %call16(__moddi3)($gp)
 
-  ; GP64-NOT-R6:  ddiv    $zero, $4, $5
-  ; GP64-NOT-R6:  teq     $5, $zero, 7
-  ; GP64-NOT-R6:  mfhi    $2
+  ; GP64-NOT-R6:      ddiv    $zero, $4, $5
+  ; GP64-NOT-R6:      teq     $5, $zero, 7
+  ; GP64-NOT-R6:      mfhi    $2
 
-  ; 64R6:         dmod    $2, $4, $5
-  ; 64R6:         teq     $5, $zero, 7
+  ; GP64-R6:          mod     $2, $4, $5
 
   %r = srem i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
 entry:
   ; ALL-LABEL: srem_i128:
 
-  ; GP32:         lw      $25, %call16(__modti3)($gp)
+    ; GP32-NOT-R6:    lw      $25, %call16(__modti3)($gp)
+    ; GP32-R6:        lw      $25, %call16(__modti3)($gp)
 
-  ; GP64-NOT-R6:  ld      $25, %call16(__modti3)($gp)
-  ; 64-R6:        ld      $25, %call16(__modti3)($gp)
+    ; GP64-NOT-R6:    ld      $25, %call16(__modti3)($gp)
+    ; GP64-R6:        ld      $25, %call16(__modti3)($gp)
 
     %r = srem i128 %a, %b
     ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/sub.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=ALL -check-prefix=GP32-NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=ALL -check-prefix=GP32-NOT-R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=ALL -check-prefix=GP64-NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=ALL -check-prefix=GP64-NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=ALL -check-prefix=GP64-NOT-R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 
 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sub_i1:
 
-  ; ALL:            subu    $[[T0:[0-9]+]], $4, $5
-  ; ALL:            sll     $[[T0]], $[[T0]], 31
-  ; ALL:            sra     $2, $[[T0]], 31
+  ; GP32:       subu    $[[T0:[0-9]+]], $4, $5
+  ; GP32:       sll     $[[T0]], $[[T0]], 31
+  ; GP32:       sra     $2, $[[T0]], 31
+
+  ; GP64:       subu    $[[T0:[0-9]+]], $4, $5
+  ; GP64:       dsll    $[[T0]], $[[T0]], 63
+  ; GP64:       dsra    $2, $[[T0]], 63
 
   %r = sub i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: sub_i8:
 
-  ; NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
-  ; NOT-R2-R6:      sll     $[[T0]], $[[T0]], 24
-  ; NOT-R2-R6:      sra     $2, $[[T0]], 24
+  ; GP32-NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
+  ; GP32-NOT-R2-R6:      sll     $[[T0]], $[[T0]], 24
+  ; GP32-NOT-R2-R6:      sra     $2, $[[T0]], 24
+
+  ; GP64-NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-NOT-R2-R6:      dsll    $[[T0]], $[[T0]], 56
+  ; GP64-NOT-R2-R6:      dsra    $2, $[[T0]], 56
 
-  ; R2-R6:          subu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:          seb     $2, $[[T0:[0-9]+]]
+  ; R2-R6:       subu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:       seb     $2, $[[T0:[0-9]+]]
 
   %r = sub i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: sub_i16:
 
-  ; NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
-  ; NOT-R2-R6:      sll     $[[T0]], $[[T0]], 16
-  ; NOT-R2-R6:      sra     $2, $[[T0]], 16
+  ; GP32-NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
+  ; GP32-NOT-R2-R6:      sll     $[[T0]], $[[T0]], 16
+  ; GP32-NOT-R2-R6:      sra     $2, $[[T0]], 16
+
+  ; GP64-NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-NOT-R2-R6:      dsll    $[[T0]], $[[T0]], 48
+  ; GP64-NOT-R2-R6:      dsra    $2, $[[T0]], 48
 
-  ; R2-R6:          subu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:          seh     $2, $[[T0:[0-9]+]]
+  ; R2-R6:       subu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:       seh     $2, $[[T0:[0-9]+]]
 
   %r = sub i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: sub_i32:
 
-  ; ALL:            subu    $2, $4, $5
+  ; GP32:       subu    $2, $4, $5
+
+  ; GP64:       subu    $[[T0:[0-9]+]], $4, $5
+  ; GP64:       sll     $2, $[[T0]], 0
 
   %r = sub i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: sub_i64:

test/CodeGen/Mips/llvm-ir/udiv.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefix=R6 -check-prefix=GP32
+; RUN:    -check-prefix=GP32-R6 -check-prefix=R6
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefix=R6 -check-prefix=64R6
+; RUN:    -check-prefix=GP64-R6 -check-prefix=R6
 
 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i1:
 
-  ; NOT-R6:       divu    $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mflo    $2
-
-  ; R6:           divu    $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP32-PRE-R6:      divu    $zero, $4, $5
+  ; GP32-PRE-R6:      teq     $5, $zero, 7
+  ; GP32-PRE-R6:      mflo    $2
+
+  ; GP64-PRE-R6:      divu    $zero, $4, $5
+  ; GP64-PRE-R6:      teq     $5, $zero, 7
+  ; GP64-PRE-R6:      mflo    $[[T0:[0-9]+]]
+  ; GP64-PRE-R6:      dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:      dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:          divu    $2, $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+
+  ; GP64-R6:          divu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since div is unsigned.
+  ; GP64-R6:          dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:          dsrl    $2, $[[T1]], 32
 
   %r = udiv i1 %a, %b
   ret i1 %r
 }
 
 define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i8:
 
-  ; NOT-R6:       divu    $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mflo    $2
-
-  ; R6:           divu    $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP32-PRE-R6:      divu    $zero, $4, $5
+  ; GP32-PRE-R6:      teq     $5, $zero, 7
+  ; GP32-PRE-R6:      mflo    $2
+
+  ; GP64-PRE-R6:      divu    $zero, $4, $5
+  ; GP64-PRE-R6:      teq     $5, $zero, 7
+  ; GP64-PRE-R6:      mflo    $[[T0:[0-9]+]]
+  ; GP64-PRE-R6:      dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:      dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:          divu    $2, $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+
+  ; GP64-R6:          divu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since div is unsigned.
+  ; GP64-R6:          dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:          dsrl    $2, $[[T1]], 32
 
   %r = udiv i8 %a, %b
   ret i8 %r
 }
 
 define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i16:
 
-  ; NOT-R6:       divu    $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mflo    $2
-
-  ; R6:           divu    $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP32-PRE-R6:      divu    $zero, $4, $5
+  ; GP32-PRE-R6:      teq     $5, $zero, 7
+  ; GP32-PRE-R6:      mflo    $2
+
+  ; GP64-PRE-R6:      divu    $zero, $4, $5
+  ; GP64-PRE-R6:      teq     $5, $zero, 7
+  ; GP64-PRE-R6:      mflo    $[[T0:[0-9]+]]
+  ; GP64-PRE-R6:      dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:      dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:          divu    $2, $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+
+  ; GP64-R6:          divu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since div is signed.
+  ; GP64-R6:          dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:          dsrl    $2, $[[T1]], 32
 
   %r = udiv i16 %a, %b
   ret i16 %r
 }
 
-define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
+define zeroext i32 @udiv_i32(i32 zeroext %a, i32 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i32:
 
-  ; NOT-R6:       divu    $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mflo    $2
-
-  ; R6:           divu    $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP32-PRE-R6:      divu    $zero, $4, $5
+  ; GP32-PRE-R6:      teq     $5, $zero, 7
+  ; GP32-PRE-R6:      mflo    $2
+
+  ; GP64-PRE-R6:      divu    $zero, $4, $5
+  ; GP64-PRE-R6:      teq     $5, $zero, 7
+  ; GP64-PRE-R6:      mflo    $[[T0:[0-9]+]]
+  ; GP64-PRE-R6:      dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:      dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:          divu    $2, $4, $5
+  ; GP32-R6:          teq     $5, $zero, 7
+
+  ; GP64-R6:          divu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
+  ; GP64-R6:          dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:          dsrl    $2, $[[T1]], 32
 
   %r = udiv i32 %a, %b
   ret i32 %r
 }
 
-define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
+define zeroext i64 @udiv_i64(i64 zeroext %a, i64 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i64:
 
-  ; GP32:         lw      $25, %call16(__udivdi3)($gp)
+  ; GP32-PRE-R6:      lw      $25, %call16(__udivdi3)($gp)
+  ; GP32-R6:          lw      $25, %call16(__udivdi3)($gp)
 
-  ; GP64-NOT-R6:  ddivu   $zero, $4, $5
-  ; GP64-NOT-R6:  teq     $5, $zero, 7
-  ; GP64-NOT-R6:  mflo    $2
+  ; GP64-PRE-R6:      ddivu   $zero, $4, $5
+  ; GP64-PRE-R6:      teq     $5, $zero, 7
+  ; GP64-PRE-R6:      mflo    $2
 
-  ; 64R6:         ddivu   $2, $4, $5
-  ; 64R6:         teq     $5, $zero, 7
+  ; GP64-R6:          ddivu   $2, $4, $5
+  ; GP64-R6:          teq     $5, $zero, 7
 
   %r = udiv i64 %a, %b
   ret i64 %r
 }
 
-define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
+define zeroext i128 @udiv_i128(i128 zeroext %a, i128 zeroext %b) {
 entry:
   ; ALL-LABEL: udiv_i128:
 
-  ; GP32:         lw      $25, %call16(__udivti3)($gp)
+    ; GP32-PRE-R6:    lw      $25, %call16(__udivti3)($gp)
+    ; GP32-R6:        lw      $25, %call16(__udivti3)($gp)
 
-  ; GP64-NOT-R6:  ld      $25, %call16(__udivti3)($gp)
-  ; 64-R6:        ld      $25, %call16(__udivti3)($gp)
+    ; GP64-PRE-R6:    ld      $25, %call16(__udivti3)($gp)
+    ; GP64-R6:        ld      $25, %call16(__udivti3)($gp)
 
     %r = udiv i128 %a, %b
     ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/urem.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:  -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP32-PRE-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN:    -check-prefix=GP32-PRE-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN:    -check-prefix=GP32-PRE-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN:    -check-prefix=GP32-PRE-R6
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:   -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=GP32-R6 -check-prefix=R6
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:  -check-prefix=R2-R5 -check-prefix=R2-R6 \
-; RUN:  -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN:    -check-prefix=GP64-PRE-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:  -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
+; RUN:    -check-prefix=GP64-R6 -check-prefix=R6
 
-define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
+define zeroext i1 @urem_i1(i1 zeroext %a, i1 zeroext %b) {
 entry:
 ; ALL-LABEL: urem_i1:
 
-  ; NOT-R6:       andi    $[[T0:[0-9]+]], $5, 1
-  ; NOT-R6:       andi    $[[T1:[0-9]+]], $4, 1
-  ; NOT-R6:       divu    $zero, $[[T1]], $[[T0]]
-  ; NOT-R6:       teq     $[[T0]], $zero, 7
-  ; NOT-R6:       mfhi    $[[T2:[0-9]+]]
-  ; NOT-R6:       sll     $[[T3:[0-9]+]], $[[T2]], 31
-  ; NOT-R6:       sra     $2, $[[T3]], 31
-
-  ; R6:           andi    $[[T0:[0-9]+]], $5, 1
-  ; R6:           andi    $[[T1:[0-9]+]], $4, 1
-  ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
-  ; R6:           teq     $[[T0]], $zero, 7
-  ; R6:           sll     $[[T3:[0-9]+]], $[[T2]], 31
-  ; R6:           sra     $2, $[[T3]], 31
+  ; GP32-PRE-R6:    divu    $zero, $4, $5
+  ; GP32-PRE-R6:    teq     $5, $zero, 7
+  ; GP32-PRE-R6:    mfhi    $2
+
+  ; GP64-PRE-R6:    divu    $zero, $4, $5
+  ; GP64-PRE-R6:    teq     $5, $zero, 7
+  ; GP64-PRE-R6:    mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The sll/sra instructions are redundant since divu is signed.
+  ; GP64-PRE-R6:    dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:    dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:        modu    $2, $4, $5
+
+  ; GP64-R6:        modu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:        teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since divu is signed.
+  ; GP64-R6:        dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:        dsrl    $2, $[[T1]], 32
 
   %r = urem i1 %a, %b
   ret i1 %r
 }
 
-define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
+define zeroext i8 @urem_i8(i8 zeroext %a, i8 zeroext %b) {
 entry:
 ; ALL-LABEL: urem_i8:
 
-  ; NOT-R2-R6:    andi    $[[T0:[0-9]+]], $5, 255
-  ; NOT-R2-R6:    andi    $[[T1:[0-9]+]], $4, 255
-  ; NOT-R2-R6:    divu    $zero, $[[T1]], $[[T0]]
-  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
-  ; NOT-R2-R6:    mfhi    $[[T2:[0-9]+]]
-  ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 24
-  ; NOT-R2-R6:    sra     $2, $[[T3]], 24
-
-  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 255
-  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 255
-  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
-  ; R2-R5:        teq     $[[T0]], $zero, 7
-  ; R2-R5:        mfhi    $[[T2:[0-9]+]]
-  ; R2-R5:        seb     $2, $[[T2]]
-
-  ; R6:           andi    $[[T0:[0-9]+]], $5, 255
-  ; R6:           andi    $[[T1:[0-9]+]], $4, 255
-  ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
-  ; R6:           teq     $[[T0]], $zero, 7
-  ; R6:           seb     $2, $[[T2]]
+  ; GP32-PRE-R6:    divu    $zero, $4, $5
+  ; GP32-PRE-R6:    teq     $5, $zero, 7
+  ; GP32-PRE-R6:    mfhi    $2
+
+  ; GP64-PRE-R6:    divu    $zero, $4, $5
+  ; GP64-PRE-R6:    teq     $5, $zero, 7
+  ; GP64-PRE-R6:    mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The sll/sra instructions are redundant since divu is signed.
+  ; GP64-PRE-R6:    dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:    dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:        modu     $2, $4, $5
+
+  ; GP64-R6:        modu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:        teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since divu is signed.
+  ; GP64-R6:        dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:        dsrl    $2, $[[T1]], 32
 
   %r = urem i8 %a, %b
   ret i8 %r
 }
 
-define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
+define zeroext i16 @urem_i16(i16 zeroext %a, i16 zeroext %b) {
 entry:
 ; ALL-LABEL: urem_i16:
 
-  ; NOT-R2-R6:    andi    $[[T0:[0-9]+]], $5, 65535
-  ; NOT-R2-R6:    andi    $[[T1:[0-9]+]], $4, 65535
-  ; NOT-R2-R6:    divu    $zero, $[[T1]], $[[T0]]
-  ; NOT-R2-R6:    teq     $[[T0]], $zero, 7
-  ; NOT-R2-R6:    mfhi    $[[T2:[0-9]+]]
-  ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 16
-  ; NOT-R2-R6:    sra     $2, $[[T3]], 16
-
-  ; R2-R5:        andi    $[[T0:[0-9]+]], $5, 65535
-  ; R2-R5:        andi    $[[T1:[0-9]+]], $4, 65535
-  ; R2-R5:        divu    $zero, $[[T1]], $[[T0]]
-  ; R2-R5:        teq     $[[T0]], $zero, 7
-  ; R2-R5:        mfhi    $[[T3:[0-9]+]]
-  ; R2-R5:        seh     $2, $[[T2]]
-
-  ; R6:           andi    $[[T0:[0-9]+]], $5, 65535
-  ; R6:           andi    $[[T1:[0-9]+]], $4, 65535
-  ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
-  ; R6:           teq     $[[T0]], $zero, 7
-  ; R6:           seh     $2, $[[T2]]
+  ; GP32-PRE-R6:    divu    $zero, $4, $5
+  ; GP32-PRE-R6:    teq     $5, $zero, 7
+  ; GP32-PRE-R6:    mfhi    $2
+
+  ; GP64-PRE-R6:    divu    $zero, $4, $5
+  ; GP64-PRE-R6:    teq     $5, $zero, 7
+  ; GP64-PRE-R6:    mfhi    $[[T0:[0-9]+]]
+  ; FIXME: The sll/sra instructions are redundant since divu is signed.
+  ; GP64-PRE-R6:    dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:    dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:        modu     $2, $4, $5
+
+  ; GP64-R6:        modu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:        teq     $5, $zero, 7
+  ; FIXME: The sll/sra instructions are redundant since divu is signed.
+  ; GP64-R6:        dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:        dsrl    $2, $[[T1]], 32
 
   %r = urem i16 %a, %b
   ret i16 %r
 }
 
-define signext i32 @urem_i32(i32 signext %a, i32 signext %b) {
+define zeroext i32 @urem_i32(i32 zeroext %a, i32 zeroext %b) {
 entry:
 ; ALL-LABEL: urem_i32:
 
-  ; NOT-R6:       divu    $zero, $4, $5
-  ; NOT-R6:       teq     $5, $zero, 7
-  ; NOT-R6:       mfhi    $2
-
-  ; R6:           modu    $2, $4, $5
-  ; R6:           teq     $5, $zero, 7
+  ; GP32-PRE-R6:    divu    $zero, $4, $5
+  ; GP32-PRE-R6:    teq     $5, $zero, 7
+  ; GP32-PRE-R6:    mfhi    $2
+
+  ; GP64-PRE-R6:    divu     $zero, $4, $5
+  ; GP64-PRE-R6:    teq     $5, $zero, 7
+  ; GP64-PRE-R6:    mfhi    $[[T0:[0-9]+]]
+  ; GP64-PRE-R6:    dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-PRE-R6:    dsrl    $2, $[[T1]], 32
+
+  ; GP32-R6:        modu    $2, $4, $5
+  ; GP32-R6:        teq     $5, $zero, 7
+
+  ; GP64-R6:        modu    $[[T0:[0-9]+]], $4, $5
+  ; GP64-R6:        teq     $5, $zero, 7
+  ; GP64-R6:        dsll    $[[T1:[0-9]+]], $[[T0]], 32
+  ; GP64-R6:        dsrl    $2, $[[T1]], 32
 
   %r = urem i32 %a, %b
   ret i32 %r
 }
 
-define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
+define zeroext i64 @urem_i64(i64 zeroext %a, i64 zeroext %b) {
 entry:
 ; ALL-LABEL: urem_i64:
 
-  ; GP32:         lw      $25, %call16(__umoddi3)($gp)
+  ; GP32-PRE-R6:    lw      $25, %call16(__umoddi3)($gp)
+  ; GP32-R6:        lw      $25, %call16(__umoddi3)($gp)
 
-  ; GP64-NOT-R6:  ddivu   $zero, $4, $5
-  ; GP64-NOT-R6:  teq     $5, $zero, 7
-  ; GP64-NOT-R6:  mfhi    $2
+  ; GP64-PRE-R6:    ddivu   $zero, $4, $5
+  ; GP64-PRE-R6:    teq     $5, $zero, 7
+  ; GP64-PRE-R6:    mfhi    $2
 
-  ; 64R6:         dmodu   $2, $4, $5
-  ; 64R6:         teq     $5, $zero, 7
+  ; GP64-R6:        modu    $2, $4, $5
 
   %r = urem i64 %a, %b
   ret i64 %r
 }
 
-define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
+define zeroext i128 @urem_i128(i128 zeroext %a, i128 zeroext %b) {
 entry:
   ; ALL-LABEL: urem_i128:
 
-    ; GP32:         lw      $25, %call16(__umodti3)($gp)
+    ; GP32-PRE-R6:  lw      $25, %call16(__umodti3)($gp)
+    ; GP32-R6:      lw      $25, %call16(__umodti3)($gp)
 
-    ; GP64-NOT-R6:  ld      $25, %call16(__umodti3)($gp)
-    ; 64-R6:        ld      $25, %call16(__umodti3)($gp)
+    ; GP64-PRE-R6:  ld      $25, %call16(__umodti3)($gp)
+    ; GP64-R6:      ld      $25, %call16(__umodti3)($gp)
 
     %r = urem i128 %a, %b
     ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/xor.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP32
+
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64
; ALL-LABEL: xor_i16:
   %r = xor i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; GP32:         xor     $2, $4, $5
-
-  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          xor     $2, $4, $5
 
   %r = xor i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: xor_i64:

test/CodeGen/Mips/msa/basic_operations.ll

define i32 @extract_sext_v16i8() nounwind {
   ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
   %2 = add <16 x i8> %1, %1
   ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <16 x i8> %2, i32 1
   %4 = sext i8 %3 to i32
   ; ALL-DAG: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
-  ; ALL-NOT: sll
-  ; ALL-NOT: sra
+  ; MIPS32-NOT: sll
+  ; MIPS32-NOT: sra
 
   ret i32 %4
 }
 
 define i32 @extract_sext_v8i16() nounwind {
   ; ALL-LABEL: extract_sext_v8i16:
 
   %1 = load <8 x i16>, <8 x i16>* @v8i16
   ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
   %2 = add <8 x i16> %1, %1
   ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <8 x i16> %2, i32 1
   %4 = sext i16 %3 to i32
   ; ALL-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
-  ; ALL-NOT: sll
-  ; ALL-NOT: sra
+  ; MIPS32-NOT: sll
+  ; MIPS32-NOT: sra
 
   ret i32 %4
 }
 
 define i32 @extract_sext_v4i32() nounwind {
   ; ALL-LABEL: extract_sext_v4i32:
 
   %1 = load <4 x i32>, <4 x i32>* @v4i32
define i32 @extract_zext_v16i8() nounwind {
   %1 = load <16 x i8>, <16 x i8>* @v16i8
   ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
   %2 = add <16 x i8> %1, %1
   ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <16 x i8> %2, i32 1
   %4 = zext i8 %3 to i32
-  ; ALL-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
-  ; ALL-NOT: andi
+  ; MIPS32-DAG: copy_u.b [[R3:\$[0-9]+]], [[R1]][1]
+  ; MIPS32-NOT: andi
+
+  ; MIPS64: copy_s.b [[R3:\$[0-9]+]], [[R1]][1]
 
   ret i32 %4
 }
 
 define i32 @extract_zext_v8i16() nounwind {
   ; ALL-LABEL: extract_zext_v8i16:
 
   %1 = load <8 x i16>, <8 x i16>* @v8i16
   ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
   %2 = add <8 x i16> %1, %1
   ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <8 x i16> %2, i32 1
   %4 = zext i16 %3 to i32
-  ; ALL-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
-  ; ALL-NOT: andi
+  ; MIPS32-DAG: copy_u.h [[R3:\$[0-9]+]], [[R1]][1]
+  ; MIPS32-NOT: andi
+
+  ; MIPS64-DAG: copy_s.h [[R3:\$[0-9]+]], [[R1]][1]
 
   ret i32 %4
 }
 
 define i32 @extract_zext_v4i32() nounwind {
   ; ALL-LABEL: extract_zext_v4i32:
 
   %1 = load <4 x i32>, <4 x i32>* @v4i32
define i32 @extract_zext_v16i8_vidx() nounwind {
   ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <16 x i8> %2, i32 %3
   %5 = zext i8 %4 to i32
   ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
+  ; MIPS32-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
+  ; MIPS64-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
+  ; MIPS64-DAG: andi $2, [[R6]], 255
 
   ret i32 %5
 }
 
 define i32 @extract_zext_v8i16_vidx() nounwind {
   ; ALL-LABEL: extract_zext_v8i16_vidx:
 
   %1 = load <8 x i16>, <8 x i16>* @v8i16
define i32 @extract_zext_v8i16_vidx() nounwind {
   ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <8 x i16> %2, i32 %3
   %5 = zext i16 %4 to i32
   ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
+  ; MIPS32-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
+  ; MIPS64-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
+  ; MIPS64-DAG: andi $2, [[R6]], 65535
 
   ret i32 %5
 }
 
 define i32 @extract_zext_v4i32_vidx() nounwind {
   ; ALL-LABEL: extract_zext_v4i32_vidx:
 
   %1 = load <4 x i32>, <4 x i32>* @v4i32

test/CodeGen/Mips/named-register-n32.ll

 ; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s | FileCheck %s
 
 define i32* @get_gp() {
 entry:
   %0 = call i64 @llvm.read_register.i64(metadata !0)
   %1 = trunc i64 %0 to i32
   %2 = inttoptr i32 %1 to i32*
   ret i32* %2
 }
 
 ; CHECK-LABEL: get_gp:
-; CHECK:           sll $2, $gp, 0
+; CHECK:           move $2, $gp
 
 declare i64 @llvm.read_register.i64(metadata)
 
 !llvm.named.register.$28 = !{!0}
 
 !0 = !{!"$28"}