[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.

[dsanders]

LGTM with the unused CHECKs and the assumption that the result of the fadd is $f0 fixed

test/CodeGen/Mips/fcopysign-f32-f64.ll

11 ↗

(On Diff #42431)

This isn't checked anymore. 'CHECK' is only the default prefix when no prefixes are given.

34 ↗

(On Diff #42431)

Likewise

36–45 ↗

(On Diff #42431)

It's not for this patch but this output doesn't seem very efficient. For example, it could clear the top bit with a dsll+dsrl saving two instructions

42 ↗

(On Diff #42431)

This $f0 isn't guaranteed to be $f0.

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
 
 // 32-to-64-bit extension
-def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
+def : MipsPat<(i64 (anyext GPR32:$src)),
+              (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 
 // Sign extend in register
 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
               (SLL64_64 GPR64:$src)>;
 
 // bswap MipsPattern

llvm/trunk/test/CodeGen/Mips/cconv/return-struct.ll

 ; sret pointer is already in $4
 ; O32-DAG:        lui [[PTR:\$[0-9]+]], %hi(struct_128xi16)
 ; O32-DAG:        addiu $5, [[PTR]], %lo(struct_128xi16)
 ; O32:            jal memcpy
 
 ; sret pointer is already in $4
 ; N32-DAG:        lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16)
 ; N32-DAG:        addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16)
-; FIXME: This signext isn't necessary. Like integers, pointers are
-;        but unlike integers, pointers cannot have the signext attribute.
-; N32-DAG:        sll $5, [[PTR]], 0
 ; N32:            jal memcpy
 
 ; sret pointer is already in $4
 ; N64-DAG:        ld $5, %got_disp(struct_128xi16)(
 ; N64-DAG:        ld $25, %call16(memcpy)(
 ; N64:            jalr $25
 
 ; Ensure that large structures (>128-bit) are returned indirectly.

llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll

-; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64
-; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2
+; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64R2
 
 declare double @copysign(double, double) nounwind readnone
 
 declare float @copysignf(float, float) nounwind readnone
 
 define float @func2(float %d, double %f) nounwind readnone {
 entry:
-; 64:     func2
+; ALL-LABEL: func2:
+
 ; 64-DAG: lui  $[[T0:[0-9]+]], 32767
 ; 64-DAG: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
 ; 64-DAG: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
 ; 64-DAG: sll  $[[SLL0:[0-9]+]], $[[DSRL]], 0
 ; 64-DAG: sll  $[[SLL1:[0-9]+]], $[[SLL0]], 31
 ; 64:     or   $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
 ; 64:     mtc1 $[[OR]], $f0
 
 ; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
 ; 64R2: ins  $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
 ; 64R2: mtc1 $[[INS]], $f0
 
   %add = fadd float %d, 1.000000e+00
   %conv = fptrunc double %f to float
   %call = tail call float @copysignf(float %add, float %conv) nounwind readnone
   ret float %call
 }
 
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
+; ALL-LABEL: func3:
 
-; 64:     func3
-; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1
-; 64-DAG: dsll   $[[T1:[0-9]+]], $[[T0]], 63
-; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
-; 64-DAG: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64-DAG: srl    $[[SRL:[0-9]+]], ${{[0-9]+}}, 31
-; 64-DAG: sll    $[[SLL:[0-9]+]], $[[SRL]], 0
-; 64-DAG: dsll   $[[DSLL:[0-9]+]], $[[SLL]], 63
-; 64:     or     $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
-; 64:     dmtc1  $[[OR]], $f0
+; 64-DAG: mfc1    $[[MFC:[0-9]+]], $f13
+; 64-DAG: srl     $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
+; 64:     dsll    $[[DSLL:[0-9]+]], $[[SRL]], 63
+; 64-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
+; 64-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
+; 64-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
+; 64-DAG: dmfc1   $[[R0:[0-9]+]], ${{.*}}
+; 64:     and     $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
+; 64:     or      $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
+; 64:     dmtc1   $[[OR]], $f0
 
 ; 64R2: ext   ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
 ; 64R2: dins  $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
 ; 64R2: dmtc1 $[[INS]], $f0
 
   %add = fadd double %d, 1.000000e+00
   %conv = fpext float %f to double
   %call = tail call double @copysign(double %add, double %conv) nounwind readnone
   ret double %call
 }
-