Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions for Thumb2

[weimingz]

Summary

r250697 fixed the mapping for ARM mode. We have to do the same for Thumb2 otherwise the same llvm.arm.ssat() will generate different saturating amount for ARM and Thumb.

r250697: http://reviews.llvm.org/rL250697

[rmaprath]

Hi Weiming,

Can you update the related out-of-range tests as well? as in http://reviews.llvm.org/rL250697?

LGTM otherwise.

[weimingz]

Hi Asiri,

Sure.

[rmaprath]

Looks like you've missed usat-lower.ll and usat-upper.ll updates? Please update them before commit. LGTM.

[weimingz]

Update tests for usat

lib/Target/ARM/ARMInstrThumb2.td

def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
   let Inst{20} = 0;
   let Inst{15} = 0;
   let Inst{21} = 1;        // sh = '1'
   let Inst{14-12} = 0b000; // imm3 = '000'
   let Inst{7-6} = 0b00;    // imm2 = '00'
   let Inst{5-4} = 0b00;
 }
 
-def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
-def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
+def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos), (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
+def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos), (t2USAT imm0_31:$pos, GPR:$a, 0)>;
 
 //===----------------------------------------------------------------------===//
 //  Shift and rotate Instructions.
 //
 
 defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm0_31,
                         BinOpFrag<(shl  node:$LHS, node:$RHS)>>;
 defm t2LSR  : T2I_sh_ir<0b01, "lsr", imm_sr,

test/CodeGen/ARM/sat-arith.ll

-; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s
+; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s -check-prefix=ARM -check-prefix=CHECK
+; RUN: llc -O1 -mtriple=thumbv7-none-none-eabi %s -o - | FileCheck %s -check-prefix=THUMB -check-prefix=CHECK
 
 ; CHECK-LABEL: qadd
 define i32 @qadd() nounwind {
-; CHECK: mov [[R0:.*]], #8
-; CHECK: mov [[R1:.*]], #128
-; CHECK: qadd [[R0]], [[R1]], [[R0]]
+; CHECK-DAG: mov{{s?}} [[R0:.*]], #8
+; CHECK-DAG: mov{{s?}} [[R1:.*]], #128
+; CHECK-ARM: qadd [[R0]], [[R1]], [[R0]]
+; CHECK-THRUMB: qadd [[R0]], [[R0]], [[R1]]
   %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
   ret i32 %tmp
 }
 
 ; CHECK-LABEL: qsub
 define i32 @qsub() nounwind {
-; CHECK: mov [[R0:.*]], #8
-; CHECK: mov [[R1:.*]], #128
-; CHECK: qsub [[R0]], [[R1]], [[R0]]
+; CHECK-DAG: mov{{s?}} [[R0:.*]], #8
+; CHECK-DAG: mov{{s?}} [[R1:.*]], #128
+; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]]
+; CHECK-THRUMB: qadd [[R0]], [[R1]], [[R0]]
   %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
   ret i32 %tmp
 }
 
 ; upper-bound of the immediate argument
 ; CHECK-LABEL: ssat1
 define i32 @ssat1() nounwind {
-; CHECK: mov [[R0:.*]], #128
+; CHECK: mov{{s?}} [[R0:.*]], #128
 ; CHECK: ssat [[R1:.*]], #32, [[R0]]
   %tmp = call i32 @llvm.arm.ssat(i32 128, i32 32)
   ret i32 %tmp
 }
 
 ; lower-bound of the immediate argument
 ; CHECK-LABEL: ssat2
 define i32 @ssat2() nounwind {
-; CHECK: mov [[R0:.*]], #128
+; CHECK: mov{{s?}} [[R0:.*]], #128
 ; CHECK: ssat [[R1:.*]], #1, [[R0]]
   %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
   ret i32 %tmp
 }
 
 ; upper-bound of the immediate argument
 ; CHECK-LABEL: usat1
 define i32 @usat1() nounwind {
-; CHECK: mov [[R0:.*]], #128
+; CHECK: mov{{s?}} [[R0:.*]], #128
 ; CHECK: usat [[R1:.*]], #31, [[R0]]
   %tmp = call i32 @llvm.arm.usat(i32 128, i32 31)
   ret i32 %tmp
 }
 
 ; lower-bound of the immediate argument
 ; CHECK-LABEL: usat2
 define i32 @usat2() nounwind {
-; CHECK: mov [[R0:.*]], #128
+; CHECK: mov{{s?}} [[R0:.*]], #128
 ; CHECK: usat [[R1:.*]], #0, [[R0]]
   %tmp = call i32 @llvm.arm.usat(i32 128, i32 0)
   ret i32 %tmp
 }
 
 declare i32 @llvm.arm.qadd(i32, i32) nounwind
 declare i32 @llvm.arm.qsub(i32, i32) nounwind
 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
 declare i32 @llvm.arm.usat(i32, i32) nounwind readnone

test/CodeGen/ARM/ssat-lower.ll

 ; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
 
 ; immediate argument < lower-bound
 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
 define i32 @ssat1() nounwind {
   %tmp = call i32 @llvm.arm.ssat(i32 128, i32 0)
   ret i32 %tmp
 }
 
 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone

test/CodeGen/ARM/ssat-upper.ll

 ; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
 
 ; immediate argument > upper-bound
 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat
 define i32 @ssat1() nounwind {
   %tmp = call i32 @llvm.arm.ssat(i32 128, i32 33)
   ret i32 %tmp
 }
 
 declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone

test/CodeGen/ARM/usat-lower.ll

 ; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
 
 ; immediate argument < lower-bound
 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat
 define i32 @usat1() nounwind {
   %tmp = call i32 @llvm.arm.usat(i32 128, i32 -1)
   ret i32 %tmp
 }
 
 declare i32 @llvm.arm.usat(i32, i32) nounwind readnone

test/CodeGen/ARM/usat-upper.ll

 ; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s
 
 ; immediate argument > upper-bound
 ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat
 define i32 @usat1() nounwind {
   %tmp = call i32 @llvm.arm.usat(i32 128, i32 32)
   ret i32 %tmp
 }
 
 declare i32 @llvm.arm.usat(i32, i32) nounwind readnone