[InstCombine] allow any pair of bitcasts to be combined

[spatel]

Summary

This change is discussed in D15392.
It should be safe to convert any pair of bitcasts into a single bitcast.

It was mentioned here:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20110829/127089.html
that we're not allowed to bitcast from an x86_mmx to some other types, but I'm not seeing any failures from that.
I can add mmx-specific regression tests to confirm if that is still a concern.

[hfinkel]

LGTM.

I can add mmx-specific regression tests to confirm if that is still a concern.

It looks like we already have these (test/CodeGen/X86/bitcast-mmx.ll and test/CodeGen/X86/mmx-bitcast.ll)

[spatel]

In D15468#308934, @hfinkel wrote:

LGTM.

I can add mmx-specific regression tests to confirm if that is still a concern.

It looks like we already have these (test/CodeGen/X86/bitcast-mmx.ll and test/CodeGen/X86/mmx-bitcast.ll)

Ah, right - I was only looking in the InstCombine test folder. Thanks!

llvm/trunk/lib/IR/Instructions.cpp

static const uint8_t CastResults[numCastOps][numCastOps] = {
     { 99,99,99, 0, 0,99,99, 0, 0,99,99, 4, 0}, // FPTrunc        |
     { 99,99,99, 2, 2,99,99,10, 2,99,99, 4, 0}, // FPExt          |
     {  1, 0, 0,99,99, 0, 0,99,99,99, 7, 3, 0}, // PtrToInt       |
     { 99,99,99,99,99,99,99,99,99,11,99,15, 0}, // IntToPtr       |
     {  5, 5, 5, 6, 6, 5, 5, 6, 6,16, 5, 1,14}, // BitCast        |
     {  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,13,12}, // AddrSpaceCast -+
   };
 
+  // TODO: This logic could be encoded into the table above and handled in the
+  // switch below.
   // If either of the casts are a bitcast from scalar to vector, disallow the
-  // merging. However, bitcast of A->B->A are allowed.
-  bool isFirstBitcast  = (firstOp == Instruction::BitCast);
-  bool isSecondBitcast = (secondOp == Instruction::BitCast);
-  bool chainedBitcast  = (SrcTy == DstTy && isFirstBitcast && isSecondBitcast);
-
-  // Check if any of the bitcasts convert scalars<->vectors.
-  if ((isFirstBitcast  && isa<VectorType>(SrcTy) != isa<VectorType>(MidTy)) ||
-      (isSecondBitcast && isa<VectorType>(MidTy) != isa<VectorType>(DstTy)))
-    // Unless we are bitcasting to the original type, disallow optimizations.
-    if (!chainedBitcast) return 0;
+  // merging. However, any pair of bitcasts are allowed.
+  bool IsFirstBitcast  = (firstOp == Instruction::BitCast);
+  bool IsSecondBitcast = (secondOp == Instruction::BitCast);
+  bool AreBothBitcasts = IsFirstBitcast && IsSecondBitcast;
+
+  // Check if any of the casts convert scalars <-> vectors.
+  if ((IsFirstBitcast  && isa<VectorType>(SrcTy) != isa<VectorType>(MidTy)) ||
+      (IsSecondBitcast && isa<VectorType>(MidTy) != isa<VectorType>(DstTy)))
+    if (!AreBothBitcasts)
+      return 0;
 
   int ElimCase = CastResults[firstOp-Instruction::CastOpsBegin]
                             [secondOp-Instruction::CastOpsBegin];
   switch (ElimCase) {
     case 0: 
       // Categorically disallowed.
       return 0;
     case 1: 

llvm/trunk/test/Transforms/InstCombine/bitcast-bitcast.ll

 }
 
 define <2 x i32> @bitcast_bitcast_s_s_v(i64 %a) {
   %bc1 = bitcast i64 %a to double
   %bc2 = bitcast double %bc1 to <2 x i32>
   ret <2 x i32> %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_s_s_v(
-; CHECK-NEXT:  %bc1 = bitcast i64 %a to double
-; CHECK-NEXT:  %bc2 = bitcast double %bc1 to <2 x i32>
+; CHECK-NEXT:  %bc2 = bitcast i64 %a to <2 x i32>
 ; CHECK-NEXT:  ret <2 x i32> %bc2
 }
 
 define double @bitcast_bitcast_s_v_s(i64 %a) {
   %bc1 = bitcast i64 %a to <2 x i32>
   %bc2 = bitcast <2 x i32> %bc1 to double
   ret double %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_s_v_s(
-; CHECK-NEXT:  %bc1 = bitcast i64 %a to <2 x i32>
-; CHECK-NEXT:  %bc2 = bitcast <2 x i32> %bc1 to double
+; CHECK-NEXT:  %bc2 = bitcast i64 %a to double
 ; CHECK-NEXT:  ret double %bc2
 }
 
 define <2 x i32> @bitcast_bitcast_s_v_v(i64 %a) {
   %bc1 = bitcast i64 %a to <4 x i16>
   %bc2 = bitcast <4 x i16> %bc1 to <2 x i32>
   ret <2 x i32> %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_s_v_v(
-; CHECK-NEXT:  %bc1 = bitcast i64 %a to <4 x i16>
-; CHECK-NEXT:  %bc2 = bitcast <4 x i16> %bc1 to <2 x i32>
+; CHECK-NEXT:  %bc2 = bitcast i64 %a to <2 x i32>
 ; CHECK-NEXT:  ret <2 x i32> %bc2
 }
 
 define i64 @bitcast_bitcast_v_s_s(<2 x i32> %a) {
   %bc1 = bitcast <2 x i32> %a to double
   %bc2 = bitcast double %bc1 to i64
   ret i64 %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_v_s_s(
-; CHECK-NEXT:  %bc1 = bitcast <2 x i32> %a to double
-; CHECK-NEXT:  %bc2 = bitcast double %bc1 to i64
+; CHECK-NEXT:  %bc2 = bitcast <2 x i32> %a to i64
 ; CHECK-NEXT:  ret i64 %bc2
 }
 
 define <4 x i16> @bitcast_bitcast_v_s_v(<2 x i32> %a) {
   %bc1 = bitcast <2 x i32> %a to double
   %bc2 = bitcast double %bc1 to <4 x i16>
   ret <4 x i16> %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_v_s_v(
-; CHECK-NEXT:  %bc1 = bitcast <2 x i32> %a to double
-; CHECK-NEXT:  %bc2 = bitcast double %bc1 to <4 x i16>
+; CHECK-NEXT:  %bc2 = bitcast <2 x i32> %a to <4 x i16>
 ; CHECK-NEXT:  ret <4 x i16> %bc2
 }
 
 define double @bitcast_bitcast_v_v_s(<2 x float> %a) {
   %bc1 = bitcast <2 x float> %a to <4 x i16>
   %bc2 = bitcast <4 x i16> %bc1 to double
   ret double %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_v_v_s(
-; CHECK-NEXT:  %bc1 = bitcast <2 x float> %a to <4 x i16>
-; CHECK-NEXT:  %bc2 = bitcast <4 x i16> %bc1 to double
+; CHECK-NEXT:  %bc2 = bitcast <2 x float> %a to double
 ; CHECK-NEXT:  ret double %bc2
 }
 
 define <2 x i32> @bitcast_bitcast_v_v_v(<2 x float> %a) {
   %bc1 = bitcast <2 x float> %a to <4 x i16>
   %bc2 = bitcast <4 x i16> %bc1 to <2 x i32>
   ret <2 x i32> %bc2
 
 ; CHECK-LABEL: @bitcast_bitcast_v_v_v(
 ; CHECK-NEXT:  %bc2 = bitcast <2 x float> %a to <2 x i32>
 ; CHECK-NEXT:  ret <2 x i32> %bc2
 }