[mips] SelectionDAGISel subclasses now follow the optimization level.

[dsanders]

Summary

It was recently discovered that, for Mips's SelectionDAGISel subclasses,
all optimization levels caused SelectionDAGISel to behave like -O2.

This change adds the necessary plumbing to initialize the optimization level.

[dsanders]

I'm not sure what to do about the test. I've preserved what it was really testing for now but I believe the intention was to test SelectionDAG and not FastISel. Unfortunately, reverting the original change that added this test (rL237153) does not change the output of SelectionDAG.

Added the author and commit-er for their opinion.

[vradosavljevic]

In D14900#294537, @dsanders wrote:

I'm not sure what to do about the test. I've preserved what it was really testing for now but I believe the intention was to test SelectionDAG and not FastISel. Unfortunately, reverting the original change that added this test (rL237153) does not change the output of SelectionDAG.

Added the author and commit-er for their opinion.

In this test we're checking that register scavenging spill slot is close to $fp, but this commit (http://reviews.llvm.org/rL238829) changed the essence of this test. Any reason why this happened?

[probinson]

In D14900#295024, @vradosavljevic wrote:

In D14900#294537, @dsanders wrote:

I'm not sure what to do about the test. I've preserved what it was really testing for now but I believe the intention was to test SelectionDAG and not FastISel. Unfortunately, reverting the original change that added this test (rL237153) does not change the output of SelectionDAG.

Added the author and commit-er for their opinion.

In this test we're checking that register scavenging spill slot is close to $fp, but this commit (http://reviews.llvm.org/rL238829) changed the essence of this test. Any reason why this happened?

The test looks likes it's trying to create enough register pressure to induce the use of the "scavenging spill slot," but that would depend on exactly what the DAG looks like and which register allocator pass you're using. The -O0/-O2 confusion, -fast-isel=false, and 'optnone' tweaks all seem to be attempts to set up exactly the right conditions. Is there a way to control pass selection more directly?

[dsanders]

In this test we're checking that register scavenging spill slot is close to $fp, but this commit (http://reviews.llvm.org/rL238829) changed the essence of this test. Any reason why this happened?

The main aim of r238829 was to correctly align vector locals on the stack since (in the O32 ABI) the maximum alignment is 8 and vectors need 16*. The test uses a few vectors so that explains why it was affected, however dynamic stack realignment reserves an additional register so I'd have thought it would make triggering the register scavenger more likely. I'll take a closer look.

*Actually, they only need element-size alignment but I don't think we can describe that and we should get better performance from 16 anyway.

[dean]

Hi,

not sure, has this functionality been merged? If not, is not it anymore needed?

[dsanders]

It hasn't been committed yet and it seems I've forgotten to ping it. I'll refresh it soon.

[dsanders]

Refresh patch and ping

[probinson]

The code changes look pretty mechanical and straightforward.
But.... *no* tests affected by this?

[dsanders]

There was one test affected in my original branch but it was the same test change as your patch and fell out when I rebased beyond your commit. I expect I can find another test case.

[dsanders]

It turns out that a very small number of decisions depend on SelectionDAGISel::OptLevel.
One of them is whether DAGCombine merges consecutive stores or not so I've added
a test case based on this.

[dsanders]

Refresh patch as discussed in post-commit comments for r274786

[andrew.w.kaylor]

LGTM

lib/Target/Mips/Mips16ISelDAGToDAG.h

 #define LLVM_LIB_TARGET_MIPS_MIPS16ISELDAGTODAG_H
 
 #include "MipsISelDAGToDAG.h"
 
 namespace llvm {
 
 class Mips16DAGToDAGISel : public MipsDAGToDAGISel {
 public:
-  explicit Mips16DAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {}
+  explicit Mips16DAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+      : MipsDAGToDAGISel(TM, OL) {}
 
 private:
   std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
                                            const SDLoc &DL, EVT Ty, bool HasLo,
                                            bool HasHi);
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
private:
 
   // Insert instructions to initialize the global base register in the
   // first MBB of the function.
   void initGlobalBaseReg(MachineFunction &MF);
 
   void initMips16SPAliasReg(MachineFunction &MF);
 };
 
-FunctionPass *createMips16ISelDag(MipsTargetMachine &TM);
+FunctionPass *createMips16ISelDag(MipsTargetMachine &TM,
+                                  CodeGenOpt::Level OptLevel);
 }
 
 #endif

lib/Target/Mips/Mips16ISelDAGToDAG.cpp

case ISD::MULHU: {
     ReplaceNode(Node, LoHi.second);
     return true;
   }
   }
 
   return false;
 }
 
-FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM) {
-  return new Mips16DAGToDAGISel(TM);
+FunctionPass *llvm::createMips16ISelDag(MipsTargetMachine &TM,
+                                        CodeGenOpt::Level OptLevel) {
+  return new Mips16DAGToDAGISel(TM, OptLevel);
 }

lib/Target/Mips/MipsISelDAGToDAG.h

 //===----------------------------------------------------------------------===//
 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
 // instructions for SelectionDAG operations.
 //===----------------------------------------------------------------------===//
 namespace llvm {
 
 class MipsDAGToDAGISel : public SelectionDAGISel {
 public:
-  explicit MipsDAGToDAGISel(MipsTargetMachine &TM)
-      : SelectionDAGISel(TM), Subtarget(nullptr) {}
+  explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+      : SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
 
   // Pass Name
   const char *getPassName() const override {
     return "MIPS DAG->DAG Pattern Instruction Selection";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 

lib/Target/Mips/MipsSEISelDAGToDAG.h

 
 #include "MipsISelDAGToDAG.h"
 
 namespace llvm {
 
 class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
 
 public:
-  explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM) : MipsDAGToDAGISel(TM) {}
+  explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
+      : MipsDAGToDAGISel(TM, OL) {}
 
 private:
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
                              MachineFunction &MF);
 
private:
   // first MBB of the function.
   void initGlobalBaseReg(MachineFunction &MF);
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                     unsigned ConstraintID,
                                     std::vector<SDValue> &OutOps) override;
 };
 
-FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM);
-
+FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
+                                  CodeGenOpt::Level OptLevel);
 }
 
 #endif

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

case InlineAsm::Constraint_ZC:
     // In all cases, 0-bit offsets are acceptable.
     OutOps.push_back(Op);
     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
     return false;
   }
   return true;
 }
 
-FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
-  return new MipsSEDAGToDAGISel(TM);
+FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
+                                        CodeGenOpt::Level OptLevel) {
+  return new MipsSEDAGToDAGISel(TM, OptLevel);
 }

lib/Target/Mips/MipsTargetMachine.cpp

if (getMipsSubtarget().os16())
     addPass(createMipsOs16Pass(getMipsTargetMachine()));
   if (getMipsSubtarget().inMips16HardFloat())
     addPass(createMips16HardFloatPass(getMipsTargetMachine()));
 }
 // Install an instruction selector pass using
 // the ISelDag to gen Mips code.
 bool MipsPassConfig::addInstSelector() {
   addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
-  addPass(createMips16ISelDag(getMipsTargetMachine()));
-  addPass(createMipsSEISelDag(getMipsTargetMachine()));
+  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
+  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
   return false;
 }
 
 void MipsPassConfig::addMachineSSAOptimization() {
   addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
   TargetPassConfig::addMachineSSAOptimization();
 }
 

test/CodeGen/Mips/selectiondag-optlevel.ll

+; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0
+; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2
+
+; At -O0, DAGCombine won't try to merge these consecutive loads but it will at
+; -O2.
+
+define void @foo() nounwind {
+entry:
+  %0 = alloca [2 x i8], align 32
+  %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0
+  store i8 1, i8* %1
+  %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1
+  store i8 1, i8* %2
+  ret void
+}
+
+; O0: addiu $[[REG:[0-9]+]], $zero, 1
+; O0-DAG: sb $[[REG]], 0($sp)
+; O0-DAG: sb $[[REG]], 1($sp)
+
+; O2: addiu $[[REG:[0-9]+]], $zero, 257
+; O2: sh $[[REG]], 0($sp)