[ARM] Enable shrink-wrapping by default

[qcolombet]

Summary

Hi,

This patch enables shrink-wrapping by default for ARM.
I have tested shrink-wrapping and no correctness problems came out or runtime regressions.
Although the gain may be small, the code looks nicer with shrink-wrapping enabled and the performance could just be better.

For the record shrink-wrapping was introduced after this review:
http://reviews.llvm.org/D9210

More information on Shrink-Wrapping:
http://lists.llvm.org/pipermail/llvm-dev/2015-May/085220.html

OK to commit?

Thanks,
-Quentin

[qcolombet]

ping.

[rengolin]

Sorry Quentin, I've been meaning to look at this for a while. Thanks for doing this. LGTM.

[qcolombet]

Thanks!
This is Committed revision 252825.

Q.

[qcolombet]

This finally landed in Committed revision 253411.

[tyomitch]

This change led to generation of invalid code on Thumb1 targets.

Attaching a reproducer. The function epilogue gets compiled into pop {r4, r5, r6, lr}, which is invalid for Thumb1; then, it's replaced with a (valid) pop {r4, r5, r6} instruction, which leaves the stack unbalanced.

broken.ll1 KBDownload

[qcolombet]

Nice catch!

Looks like we could produce an error when we see this kind of assembly.

Q.

[qcolombet]

Hi Artyom,

Unless I am mistaken, http://reviews.llvm.org/D14986 fixes that problem, right?

I have added a couple of comments there.

Cheers,
Q.

lib/Target/ARM/ARMFrameLowering.h

int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
                                  unsigned &FrameReg, int SPAdj) const;
 
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
 
   void adjustForSegmentedStacks(MachineFunction &MF,
                                 MachineBasicBlock &MBB) const override;
 
+  /// Returns true if the target will correctly handle shrink wrapping.
+  bool enableShrinkWrapping(const MachineFunction &MF) const override {
+    return true;
+  }
+
  private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,
                     unsigned StrOpc, bool NoGap,
                     bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs,
                     unsigned MIFlags = 0) const;
   void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                    const std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc,

test/CodeGen/ARM/call-tc.ll

 
 ; Make sure the tail call instruction isn't deleted
 ; rdar://8309338
 declare void @foo() nounwind
 
 define void @t7() nounwind {
 entry:
 ; CHECKT2D-LABEL: t7:
-; CHECKT2D: blxeq _foo
-; CHECKT2D-NEXT: pop.w
-; CHECKT2D-NEXT: b.w _foo
+; CHECKT2D: it ne
+; CHECKT2D-NEXT: bne.w _foo
+; CHECKT2D-NEXT: push
+; CHECKT2D-NEXT: mov r7, sp
+; CHECKT2D-NEXT: blx _foo
   br i1 undef, label %bb, label %bb1.lr.ph
 
 bb1.lr.ph:
   tail call void @foo() nounwind
   unreachable
 
 bb:
   tail call void @foo() nounwind

test/CodeGen/ARM/fold-stack-adjust.ll

-; RUN: llc -mtriple=thumbv7-apple-none-macho < %s | FileCheck %s
+; Disable shrink-wrapping on the first test otherwise we wouldn't
+; exerce the path for PR18136.
+; RUN: llc -mtriple=thumbv7-apple-none-macho < %s -enable-shrink-wrap=false | FileCheck %s
 ; RUN: llc -mtriple=thumbv6m-apple-none-macho -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1
 ; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS
 ; RUN: llc -mtriple=thumbv7--linux-gnueabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-LINUX
 
 
 declare void @bar(i8*)
 
 %bigVec = type [2 x double]

test/CodeGen/ARM/ifcvt5.ll

 ; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
 ; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift     | FileCheck %s -check-prefix=SWIFT
 ; rdar://8402126
 
 @x = external global i32*   ; <i32**> [#uses=1]
 
 define void @foo(i32 %a) {
 entry:
   %tmp = load i32*, i32** @x    ; <i32*> [#uses=1]
   store i32 %a, i32* %tmp
   ret void
 }
 
 define i32 @t1(i32 %a, i32 %b) {
 ; A8-LABEL: t1:
-; A8: poplt {r7, pc}
+; A8: bxlt lr
 
 ; SWIFT-LABEL: t1:
-; SWIFT: pop {r7, pc}
+; SWIFT: bxlt lr
 ; SWIFT: pop {r7, pc}
 entry:
   %tmp1 = icmp sgt i32 %a, 10    ; <i1> [#uses=1]
   br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:    ; preds = %entry
   tail call void @foo( i32 %b )
   ret i32 0
 
 UnifiedReturnBlock:   ; preds = %entry
   ret i32 1
 }

test/CodeGen/ARM/ifcvt6.ll

 ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
 
 define void @foo(i32 %X, i32 %Y) {
 entry:
 ; CHECK: cmpne
-; CHECK: pophi
+; CHECK: bxhi lr
   %tmp1 = icmp ult i32 %X, 4    ; <i1> [#uses=1]
   %tmp4 = icmp eq i32 %Y, 0    ; <i1> [#uses=1]
   %tmp7 = or i1 %tmp4, %tmp1    ; <i1> [#uses=1]
   br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:    ; preds = %entry
   %tmp10 = call i32 (...) @bar( )    ; <i32> [#uses=0]
   ret void
 
 UnifiedReturnBlock:   ; preds = %entry
   ret void
 }
 
 declare i32 @bar(...)

test/CodeGen/ARM/ifcvt8.ll

 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
 
   %struct.SString = type { i8*, i32, i32 }
 
 declare void @abort()
 
 define fastcc void @t(%struct.SString* %word, i8 signext  %c) {
-; CHECK: popne
+; CHECK-NOT: pop
+; CHECK: bxne
+; CHECK-NOT: pop
 entry:
   %tmp1 = icmp eq %struct.SString* %word, null    ; <i1> [#uses=1]
   br i1 %tmp1, label %cond_true, label %cond_false
 
 cond_true:    ; preds = %entry
   tail call void @abort( )
   unreachable
 
 cond_false:   ; preds = %entry
   ret void
 }

test/CodeGen/ARM/machine-cse-cmp.ll

 @bar = external global [250 x i8], align 1
 
 ; CSE of cmp across BB boundary
 ; rdar://10660865
 define void @f2() nounwind ssp {
 entry:
 ; CHECK-LABEL: f2:
 ; CHECK: cmp
-; CHECK: poplt
+; CHECK: bxlt
 ; CHECK-NOT: cmp
 ; CHECK: movle
   %0 = load i32, i32* @foo, align 4
   %cmp28 = icmp sgt i32 %0, 0
   br i1 %cmp28, label %for.body.lr.ph, label %for.cond1.preheader
 
 for.body.lr.ph:                                   ; preds = %entry
   %1 = icmp sgt i32 %0, 1

test/CodeGen/ARM/thumb-alignment.ll

 @b = external global i32
 @c = external global i32
 @d = external global i32
 
 ; Create a Thumb-2 jump table, which should force alignment to 4 bytes.
 
 ; CHECK: .globl baz
 ; CHECK-NEXT: .align  2
-; CHECK: adr.w
+; CHECK: tbb
 define i32 @baz() {
   %1 = load i32, i32* @c, align 4
   switch i32 %1, label %7 [
     i32 1, label %2
     i32 4, label %5
     i32 9, label %5
     i32 3, label %8
   ]

test/CodeGen/Thumb2/ifcvt-compare.ll

 
 f:
   ret void
 }
 
 define void @f1(i32 %x) optsize {
   ; CHECK-LABEL: f1:
   ; CHECK: cmp r0, #1
-  ; CHECK: it eq
+  ; CHECK: it ne
+  ; CHECK-NEXT: bxne lr
   %p = icmp eq i32 %x, 1
   br i1 %p, label %t, label %f
 
 t:
   call void @x()
   br label %f
 
 f:
   ret void
 }
 
 define void @f2(i32 %x) {
   ; CHECK-LABEL: f2:
   ; CHECK: cmp r0, #0
-  ; CHECK: it eq
+  ; CHECK: it ne
+  ; CHECK-NEXT: bxne lr
   %p = icmp eq i32 %x, 0
   br i1 %p, label %t, label %f
 
 t:
   call void @x()
   br label %f
 
 f:
   ret void
 }

test/CodeGen/Thumb2/thumb2-ifcvt1.ll

entry:
   %tmp = load i32*, i32** @x    ; <i32*> [#uses=1]
   store i32 %a, i32* %tmp
   ret void
 }
 
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
 ; CHECK-LABEL: t3:
-; CHECK: itt ge
-; CHECK: movge r0, r1
-; CHECK: blge  {{_?}}foo
+; CHECK: it lt
+; CHECK-NEXT: bxlt lr
+; CHECK: mov r0, r1
+; CHECK: bl  {{_?}}foo
   %tmp1 = icmp sgt i32 %a, 10    ; <i1> [#uses=1]
   br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:    ; preds = %entry
   call void @foo( i32 %b )
   ret void
 
 UnifiedReturnBlock:   ; preds = %entry
   ret void
 }

test/CodeGen/Thumb2/thumb2-ifcvt2.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-atomic-cfg-tidy=0 -arm-default-it | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv8-apple-ios -arm-atomic-cfg-tidy=0 -arm-no-restrict-it | FileCheck %s
 
 define void @foo(i32 %X, i32 %Y) {
 entry:
 ; CHECK-LABEL: foo:
 ; CHECK: it ne
 ; CHECK: cmpne
 ; CHECK: it hi
-; CHECK: pophi {r7, pc}
+; CHECK: bxhi lr
   %tmp1 = icmp ult i32 %X, 4    ; <i1> [#uses=1]
   %tmp4 = icmp eq i32 %Y, 0    ; <i1> [#uses=1]
   %tmp7 = or i1 %tmp4, %tmp1    ; <i1> [#uses=1]
   br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
 
 cond_true:    ; preds = %entry
   %tmp10 = call i32 (...) @bar( )    ; <i32> [#uses=0]
   ret void
return:   ; preds = %tailrecurse
   %struct.SString = type { i8*, i32, i32 }
 
 declare void @abort()
 
 define fastcc void @t1(%struct.SString* %word, i8 signext  %c) {
 entry:
 ; CHECK-LABEL: t1:
 ; CHECK: it ne
-; CHECK: popne {r7, pc}
+; CHECK: bxne lr
   %tmp1 = icmp eq %struct.SString* %word, null    ; <i1> [#uses=1]
   br i1 %tmp1, label %cond_true, label %cond_false
 
 cond_true:    ; preds = %entry
   tail call void @abort( )
   unreachable
 
 cond_false:   ; preds = %entry

test/CodeGen/Thumb2/v8_IT_5.ll

 ; RUN: llc < %s -mtriple=thumbv8 -arm-atomic-cfg-tidy=0 | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv7 -arm-atomic-cfg-tidy=0 -arm-restrict-it | FileCheck %s
 ; CHECK: it ne
 ; CHECK-NEXT: cmpne
 ; CHECK-NEXT: bne [[JUMPTARGET:.LBB[0-9]+_[0-9]+]]
 ; CHECK: cbz
 ; CHECK-NEXT: %if.else163
 ; CHECK-NEXT: mov.w
 ; CHECK-NEXT: b
 ; CHECK: [[JUMPTARGET]]:{{.*}}%if.else173
 ; CHECK-NEXT: mov.w
-; CHECK-NEXT: pop
+; CHECK-NEXT: bx lr
 ; CHECK-NEXT: %if.else145
 ; CHECK-NEXT: mov.w
 
 %struct.hc = type { i32, i32, i32, i32 }
 
 define i32 @t(i32 %type) optsize {
 entry:
   br i1 undef, label %if.then, label %if.else