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Differential D14143

[3/4] Allow SP in rGPR, starting from ARMv8 (disassembly)
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Authored by tyomitch on Oct 28 2015, 3:08 AM.

Details

Reviewers
rengolin
jmolloy

Diff Detail

Event Timeline

tyomitch updated this revision to Diff 38641.Oct 28 2015, 3:08 AM
tyomitch retitled this revision from to [3/4] Allow SP in rGPR, starting from ARMv8 (disassembly).
tyomitch added reviewers: jmolloy, rengolin.
tyomitch added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptOct 28 2015, 3:08 AM
rengolin added inline comments.Oct 28 2015, 4:00 AM
test/MC/Disassembler/ARM/invalid-thumbv7.txt
363

Out of curiosity, what changes from commas to spaces here?

test/MC/Disassembler/ARM/thumb-v8.txt
2

Nice trick! :)

tyomitch added inline comments.Oct 28 2015, 4:07 AM
test/MC/Disassembler/ARM/invalid-thumbv7.txt
363

Just for consistency with all other test cases in this file.

rengolin accepted this revision.Oct 28 2015, 4:09 AM
rengolin edited edge metadata.

LGTM. Thanks!

test/MC/Disassembler/ARM/invalid-thumbv7.txt
363

Ok, makes sense.

This revision is now accepted and ready to land.Oct 28 2015, 4:09 AM
tyomitch closed this revision.Oct 28 2015, 7:28 AM

Merged into r251516

Revision Contents

PathSize
lib/
Target/
ARM/
Disassembler/
9 lines
test/
MC/
Disassembler/
ARM/
23 lines
10 lines

Diff 38641

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Show First 20 Lines • Show All 960 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Inst.addOperand(MCOperand::createReg(Register)); Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
if (RegNo == 13 || RegNo == 15)
const FeatureBitset &featureBits =
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
S = MCDisassembler::SoftFail; S = MCDisassembler::SoftFail;
Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
return S; return S;
} }
static const uint16_t SPRDecoderTable[] = { static const uint16_t SPRDecoderTable[] = {
ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S8, ARM::S9, ARM::S10, ARM::S11,
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success; DecodeStatus S = MCDisassembler::Success;
unsigned Rm = fieldFromInstruction(Val, 0, 4); unsigned Rm = fieldFromInstruction(Val, 0, 4);
unsigned type = fieldFromInstruction(Val, 5, 2); unsigned type = fieldFromInstruction(Val, 5, 2);
unsigned imm = fieldFromInstruction(Val, 7, 5); unsigned imm = fieldFromInstruction(Val, 7, 5);
// Register-immediate // Register-immediate
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl; ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) { switch (type) {
case 0: case 0:
Shift = ARM_AM::lsl; Shift = ARM_AM::lsl;
break; break;
case 1: case 1:
▲ Show 20 Lines • Show All 4,022 Lines • Show Last 20 Lines

test/MC/Disassembler/ARM/invalid-thumbv7.txt

# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s # RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
# RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
# This file is checking Thumbv7 encodings which are globally invalid, usually due # This file is checking Thumbv7 encodings which are globally invalid, usually due
# to the constraints of the instructions not being met. For example invalid # to the constraints of the instructions not being met. For example invalid
# combinations of registers. # combinations of registers.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Undefined encoding for b.cc # Undefined encoding for b.cc
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
▲ Show 20 Lines • Show All 344 Lines • ▼ Show 20 Lines
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Unpredictable STMs # Unpredictable STMs
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# 32-bit Thumb STM instructions cannot have a writeback register which appears # 32-bit Thumb STM instructions cannot have a writeback register which appears
# in the list. # in the list.
[0xa1,0xe8,0x07,0x04] [0xa1 0xe8 0x07 0x04]
rengolinUnsubmitted
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Out of curiosity, what changes from commas to spaces here?

rengolin: Out of curiosity, what changes from commas to spaces here?
tyomitchAuthorUnsubmitted
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Just for consistency with all other test cases in this file.

tyomitch: Just for consistency with all other test cases in this file.
rengolinUnsubmitted
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Ok, makes sense.

rengolin: Ok, makes sense.
# CHECK: warning: potentially undefined instruction encoding # CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] # CHECK-NEXT: [0xa1 0xe8 0x07 0x04]
[0x21,0xe9,0x07,0x04] [0x21 0xe9 0x07 0x04]
# CHECK: warning: potentially undefined instruction encoding # CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: [0x21,0xe9,0x07,0x04] # CHECK-NEXT: [0x21 0xe9 0x07 0x04]
#------------------------------------------------------------------------------
# SP is invalid as rGPR before ARMv8
#------------------------------------------------------------------------------
[0x00 0xf0 0x00 0x0d]
# CHECK-V7: warning: potentially undefined instruction encoding
# CHECK-V7-NEXT: [0x00 0xf0 0x00 0x0d]
[0x63 0xeb 0x2d 0x46]
# CHECK-V7: warning: potentially undefined instruction encoding
# CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]

test/MC/Disassembler/ARM/thumb-v8.txt

# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding < %s | FileCheck %s # RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding 2>%t < %s | FileCheck %s
# RUN: FileCheck -allow-empty -check-prefix=STDERR < %t %s
rengolinUnsubmitted
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Nice trick! :)

rengolin: Nice trick! :)
0x80 0xba 0x80 0xba
# CHECK: hlt #0 # CHECK: hlt #0
0xbf 0xba 0xbf 0xba
# CHECK: hlt #63 # CHECK: hlt #63
# DCPS{1,2,3} # DCPS{1,2,3}
Show All 11 Lines
0xbf 0xf3 0x51 0x8f 0xbf 0xf3 0x51 0x8f
0xbf 0xf3 0x55 0x8f 0xbf 0xf3 0x55 0x8f
0xbf 0xf3 0x5d 0x8f 0xbf 0xf3 0x5d 0x8f
# CHECK: dmb ishld # CHECK: dmb ishld
# CHECK: dmb oshld # CHECK: dmb oshld
# CHECK: dmb nshld # CHECK: dmb nshld
# CHECK: dmb ld # CHECK: dmb ld
[0x00 0xf0 0x00 0x0d]
[0x63 0xeb 0x2d 0x46]
# CHECK: and sp, r0, #0
# CHECK: sbc.w r6, r3, sp, asr #16
# STDERR-NOT: warning