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Differential D13967

AMDGPU: Don't reserve SCRATCH_PTR input register
ClosedPublic

Authored by arsenm on Oct 21 2015, 6:17 PM.

Details

Reviewers
• tstellarAMD
arsenm
Summary

I don't think this has been doing anything since using relocations was added.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 38068.Oct 21 2015, 6:17 PM
arsenm retitled this revision from to AMDGPU: Don't reserve SCRATCH_PTR input register.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptOct 21 2015, 6:17 PM
arsenm added a child revision: D13873: AMDGPU: Rename enums to be consistent with HSA code object terminology.Oct 21 2015, 6:17 PM
arsenm accepted this revision.Nov 30 2015, 7:49 AM
arsenm added a reviewer: arsenm.

r254304

This revision is now accepted and ready to land.Nov 30 2015, 7:49 AM
arsenm closed this revision.Nov 30 2015, 7:50 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
10 lines
test/
CodeGen/
AMDGPU/
2 lines

Diff 38068

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 590 Lines • ▼ Show 20 Lines if (Info->getShaderType() == ShaderType::COMPUTE) {
unsigned InputPtrReg = unsigned InputPtrReg =
TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR); TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
unsigned InputPtrRegLo = unsigned InputPtrRegLo =
TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0); TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
unsigned InputPtrRegHi = unsigned InputPtrRegHi =
TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1); TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
unsigned ScratchPtrReg =
TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
unsigned ScratchPtrRegLo =
TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
unsigned ScratchPtrRegHi =
TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
CCInfo.AllocateReg(InputPtrRegLo); CCInfo.AllocateReg(InputPtrRegLo);
CCInfo.AllocateReg(InputPtrRegHi); CCInfo.AllocateReg(InputPtrRegHi);
CCInfo.AllocateReg(ScratchPtrRegLo);
CCInfo.AllocateReg(ScratchPtrRegHi);
MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
if (Subtarget->isAmdHsaOS()) { if (Subtarget->isAmdHsaOS()) {
unsigned DispatchPtrReg = unsigned DispatchPtrReg =
TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR); TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR);
unsigned DispatchPtrRegLo = unsigned DispatchPtrRegLo =
TRI->getPhysRegSubReg(DispatchPtrReg, &AMDGPU::SReg_32RegClass, 0); TRI->getPhysRegSubReg(DispatchPtrReg, &AMDGPU::SReg_32RegClass, 0);
unsigned DispatchPtrRegHi = unsigned DispatchPtrRegHi =
TRI->getPhysRegSubReg(DispatchPtrReg, &AMDGPU::SReg_32RegClass, 1); TRI->getPhysRegSubReg(DispatchPtrReg, &AMDGPU::SReg_32RegClass, 1);
CCInfo.AllocateReg(DispatchPtrRegLo); CCInfo.AllocateReg(DispatchPtrRegLo);
▲ Show 20 Lines • Show All 1,776 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll

; RUN: llc -o /dev/null %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos 2>&1 | FileCheck %s ; RUN: llc -o /dev/null %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos 2>&1 | FileCheck %s
; This test verifies that the instruction selection will add the implicit ; This test verifies that the instruction selection will add the implicit
; register operands in the correct order when modifying the opcode of an ; register operands in the correct order when modifying the opcode of an
; instruction to V_ADD_I32_e32. ; instruction to V_ADD_I32_e32.
; CHECK: %19 = V_ADD_I32_e32 %13, %12, implicit-def %vcc, implicit %exec ; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec
define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry: entry:
%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
%a = load i32, i32 addrspace(1)* %in %a = load i32, i32 addrspace(1)* %in
%b = load i32, i32 addrspace(1)* %b_ptr %b = load i32, i32 addrspace(1)* %b_ptr
%result = add i32 %a, %b %result = add i32 %a, %b
store i32 %result, i32 addrspace(1)* %out store i32 %result, i32 addrspace(1)* %out
ret void ret void
} }