LegalizeDAG: Implement promote for build_vector

[arsenm]

Summary

This will be used in future commits for AMDGPU to promote
operations on i64 vectors into operations on 32-bit vector
components.

[qcolombet]

Hi Matt,

That does not seem generally profitable and make the representation more complicate in my opinion.
That being said, I do not see tests changes here. Does this mean the change is neutral for the in tree targets or that the tests are not covering this code?

Thanks,
-Quentin

[arsenm]

In D13709#266477, @qcolombet wrote:

Hi Matt,

That does not seem generally profitable and make the representation more complicate in my opinion.
That being said, I do not see tests changes here. Does this mean the change is neutral for the in tree targets or that the tests are not covering this code?

Thanks,
-Quentin

This isn't an optimization, and no in tree target is attempting to use Promote for build_vector currently. AMDGPU already has tests that cover this which will use this in a future commit when I add v2i64 and v2f64 as legal types.

[qcolombet]

This isn't an optimization, and no in tree target is attempting to use Promote for build_vector currently.

Thanks for the clarifications. I was wondering if that new format makes sense as the canonical representation of that promotion. Now, when checking what we do for shuffles, it seems consistent so I guess this is fine.

LGTM.

Cheers,
-Quentin

[arsenm]

r250945

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
   case ISD::FEXP:
   case ISD::FEXP2: {
     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
     Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
     Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
                                   Tmp2, DAG.getIntPtrConstant(0, dl)));
     break;
   }
+  case ISD::BUILD_VECTOR: {
+    MVT EltVT = OVT.getVectorElementType();
+    MVT NewEltVT = NVT.getVectorElementType();
+
+    // Handle bitcasts to a different vector type with the same total bit size
+    //
+    // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
+    //  =>
+    //  v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
+
+    assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
+           "Invalid promote type for build_vector");
+    assert(NewEltVT.bitsLT(EltVT) && "not handled");
+
+    unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
+    MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
+    assert(TLI.isTypeLegal(MidVT) && "unexpected");
+
+    SmallVector<SDValue, 8> NewOps;
+    for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
+      SDValue Op = Node->getOperand(I);
+      NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
+    }
+
+    SDLoc SL(Node);
+    SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
+    SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
+    Results.push_back(CvtVec);
+    break;
+  }
   }
 
   // Replace the original node with the legalized result.
   if (!Results.empty())
     ReplaceNode(Node, Results.data());
 }
 
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