[ELF2] Add a base set of PPC64 relocations

[hfinkel]

Summary

This is mostly an adaptation of the code in LLVM's lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp, and handles a sufficient number of relocations to link a 'hello world' program on big-Endian PPC64/Linux (ELF v1 ABI) (and said program will even run when a few later patches are also applied).

This is obviously still missing test cases; I'm working on those. Other feedback, and suggestions on which tests to emulate, is certainly appreciated.

[ruiu]

ELF/Target.cpp

206

I'm not entirely sure, but the capitalization rule is usually applyPPCLo (not applyPPClo), no?

206–230

No need for inline. Compilers should take care of them.

208

Arguments must start with uppercase, so Value. But I prefer just V, so that we can write these functions one line.

212

No space before '('

252–253

I wouldn't write zeros beforehand. Instead, you can add as many "0, 0 , 0, ..." as you want at end of Insts to fill the entire space with zeros.

258

Remove this blank line.

267–281

I wouldn't construct Insts. Instead I'd do

write32be(Buf, 0xf810000u); // std %r2 ...
write32be(Buf + 4, 0x3d62000u | apply...)
write32be(Buf + 8, ...

287–293

if (Type != R_PPC64_REL24)
  return false;
return S.isShared() || (S....

294–295

BaseAddr -> Base

298

Rename Addend -> A, just like the ELF spec.

298–299

Offset -> Off

301–321

This switch statement enclosed with if-else-if looks a bit weird. Can you remove outer if and just use switch instead?

318–321

You want to move this piece of code just after "uint8_t *Loc = Buf + Offset;" to return early.

332

This style is not in line with others. Please don't put break after }

358

If you can trigger this assertion by giving broken object files, this shouldn't be an assert() but an error().

360

All variable must starts with uppercase.

393–397

Generally we have lots of very similar expressions to calculate relocation values, we want to write them down as simple as possible. So I don't want to use descriptive names for each temporary variables. Please use one-letter variables or don't use variables at all. For example, I'd write this as

int32_t V = int32(SymVA - Base + Off + A);
if (SignExtend32<32>(V) != V)
  error(...)
write32be(Loc, V);

(By the way, the above error check seems odd. It would never fail, no?)

400–402

write64be(Loc, SymVA - BaseAddr - Offset + Addend);

[hfinkel]

ELF/Target.cpp

206

Done.

206–230

Done.

208

Done.

212

Done.

252–253

Done.

258

Done.

267–281

Done.

287–293

Done.

294–295

BaseAddr is consistent with the names used by the other targets (we can certainly rename them all as a separate change).

298

Done.

298–299

Done.

301–321

It is done this way to share the addend-adjustment logic. Early-return: done.

332

Done.

358

Done.

360

Done.

393–397

Done.

You're right (I copied these checks from RuntimeDyldELF.cpp, and I should fix them up there as well).

400–402

I've changed everything to use similar short variable names to those that AArch64 uses.

[ruiu]

Can you upload the new patch? Thanks!

[hfinkel]

In D13562#264243, @ruiu wrote:

Can you upload the new patch? Thanks!

Yes; I'm working on some regression tests now.

[hfinkel]

Updated to reflect reviewer comments and add a regression test.

[ruiu]

Can you upload the new patch? Thanks!

ELF/Target.cpp

232

Add a blank line before this line.

232

This class does not use any members of the class, so let's make it a static non-member function.

250

Blank line.

260

Drop 'u' suffix.

263–264

Can this fit in one line if you use a shorter name for EntryOffset?

270

Blank line.

286

Blank line.

316–321

Write like this to remove the outer if.

case R_PPC64_TOC16: Type = R_PPC64_ADDR16; A -= getTocBase(); break;
case ...

319

(R) & ~3 -> R & ~3

321

You don't need {} here. {} is used in switch-case to create a new scope for local variables, but you didn't define any in this {}.

328

Ditto

349

Remove {}

352

*(L + 3) -> L[3]

353

Ditto

357

Ditto

363

Ditto

376

Ditto

380

Ditto

[hfinkel]

Addressed review comments.

[ruiu]

LGTM with nits. Thank you for your work for PPC64!

ELF/Target.cpp

218

You can remove &0xffff because least significant 48 bits are already 0.

221

Ditto

[hfinkel]

r250101, thanks!

ELF/Target.cpp

case R_X86_64_32S:
     break;
   }
   default:
     error(Twine("unrecognized reloc ") + Twine(Type));
     break;
   }
 }
 
+// Relocation masks following the #lo(value), #hi(value), #ha(value),
+// #higher(value), #highera(value), #highest(value), and #highesta(value)
+// macros defined in section 4.5.1. Relocation Types of the PPC-elf64abi
+// document.
+
+static uint16_t applyPPCLo(uint64_t V) { return V & 0xffff; }
+
+static uint16_t applyPPCHi(uint64_t V) { return (V >> 16) & 0xffff; }
+
+static uint16_t applyPPCHa(uint64_t V) { return ((V + 0x8000) >> 16) & 0xffff; }
+
+static uint16_t applyPPCHigher(uint64_t V) { return (V >> 32) & 0xffff; }
+
+static uint16_t applyPPCHighera(uint64_t V) {
+  return ((V + 0x8000) >> 32) & 0xffff;
+}
+
+static uint16_t applyPPCHighest(uint64_t V) { return (V >> 48) & 0xffff; }
+
+static uint16_t applyPPCHighesta(uint64_t V) {
+  return ((V + 0x8000) >> 48) & 0xffff;
+}
+
 PPC64TargetInfo::PPC64TargetInfo() {
-  // PCRelReloc = FIXME
-  // GotReloc = FIXME
+  PCRelReloc = R_PPC64_REL24;
+  GotReloc = R_PPC64_GLOB_DAT;
+  GotRefReloc = R_PPC64_REL64;
   PltEntrySize = 32;
   PageSize = 65536;
   VAStart = 0x10000000;
 }
+
+static uint64_t getPPC64TocBase() {
+  // The TOC consists of sections .got, .toc, .tocbss, .plt in that
+  // order. The TOC starts where the first of these sections starts.
+
+  // FIXME: This obviously does not do the right thing when there is no .got
+  // section, but there is a .toc or .tocbss section.
+  uint64_t TocVA = Out<ELF64BE>::Got->getVA();
+  if (!TocVA)
+    TocVA = Out<ELF64BE>::Plt->getVA();
+
+  // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
+  // thus permitting a full 64 Kbytes segment. Note that the glibc startup
+  // code (crt1.o) assumes that you can get from the TOC base to the
+  // start of the .toc section with only a single (signed) 16-bit relocation.
+  return TocVA + 0x8000;
+}
+
 void PPC64TargetInfo::writePltEntry(uint8_t *Buf, uint64_t GotEntryAddr,
-                                    uint64_t PltEntryAddr) const {}
+                                    uint64_t PltEntryAddr) const {
+  uint64_t Off = GotEntryAddr - getPPC64TocBase();
+
+  // FIXME: What we should do, in theory, is get the offset of the function
+  // descriptor in the .opd section, and use that as the offset from %r2 (the
+  // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
+  // be a pointer to the function descriptor in the .opd section. Using
+  // this scheme is simpler, but requires an extra indirection per PLT dispatch.
+
+  write32be(Buf,      0xf8410000);                   // std %r2, 40(%r1)
+  write32be(Buf + 4,  0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
+  write32be(Buf + 8,  0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
+  write32be(Buf + 12, 0xe96c0000);                   // ld %r11,0(%r12)
+  write32be(Buf + 16, 0x7d6903a6);                   // mtctr %r11
+  write32be(Buf + 20, 0xe84c0008);                   // ld %r2,8(%r12)
+  write32be(Buf + 24, 0xe96c0010);                   // ld %r11,16(%r12)
+  write32be(Buf + 28, 0x4e800420);                   // bctr
+}
+
 bool PPC64TargetInfo::relocNeedsGot(uint32_t Type, const SymbolBody &S) const {
-  return false;
+  if (relocNeedsPlt(Type, S))
+    return true;
+
+  switch (Type) {
+  default: return false;
+  case R_PPC64_GOT16:
+  case R_PPC64_GOT16_LO:
+  case R_PPC64_GOT16_HI:
+  case R_PPC64_GOT16_HA:
+  case R_PPC64_GOT16_DS:
+  case R_PPC64_GOT16_LO_DS:
+    return true;
+  }
 }
+
 bool PPC64TargetInfo::relocNeedsPlt(uint32_t Type, const SymbolBody &S) const {
+  if (Type != R_PPC64_REL24)
     return false;
+
+  // These are function calls that need to be redirected through a PLT stub.
+  return S.isShared() || (S.isUndefined() && S.isWeak());
 }
+
 void PPC64TargetInfo::relocateOne(uint8_t *Buf, const void *RelP, uint32_t Type,
                                   uint64_t BaseAddr, uint64_t SymVA) const {
   typedef ELFFile<ELF64BE>::Elf_Rela Elf_Rela;
   auto &Rel = *reinterpret_cast<const Elf_Rela *>(RelP);
 
-  uint64_t Offset = Rel.r_offset;
-  uint8_t *Loc = Buf + Offset;
+  uint8_t *L = Buf + Rel.r_offset;
+  uint64_t S = SymVA;
+  int64_t A = Rel.r_addend;
+  uint64_t P = BaseAddr + Rel.r_offset;
+  uint64_t TB = getPPC64TocBase();
+
+  if (Type == R_PPC64_TOC) {
+    write64be(L, TB);
+    return;
+  }
+
+  // For a TOC-relative relocation, adjust the addend and proceed in terms of
+  // the corresponding ADDR16 relocation type.
   switch (Type) {
-  case R_PPC64_ADDR64:
-    write64be(Loc, SymVA + Rel.r_addend);
+  case R_PPC64_TOC16:       Type = R_PPC64_ADDR16;       A -= TB; break;
+  case R_PPC64_TOC16_DS:    Type = R_PPC64_ADDR16_DS;    A -= TB; break;
+  case R_PPC64_TOC16_LO:    Type = R_PPC64_ADDR16_LO;    A -= TB; break;
+  case R_PPC64_TOC16_LO_DS: Type = R_PPC64_ADDR16_LO_DS; A -= TB; break;
+  case R_PPC64_TOC16_HI:    Type = R_PPC64_ADDR16_HI;    A -= TB; break;
+  case R_PPC64_TOC16_HA:    Type = R_PPC64_ADDR16_HA;    A -= TB; break;
+  default: break;
+  }
+
+  uint64_t R = S + A;
+
+  switch (Type) {
+  case R_PPC64_ADDR16:
+    write16be(L, applyPPCLo(R));
+    break;
+  case R_PPC64_ADDR16_DS:
+    if (!isInt<16>(R))
+      error("Relocation R_PPC64_ADDR16_DS overflow");
+    write16be(L, (read16be(L) & 3) | (R & ~3));
+    break;
+  case R_PPC64_ADDR16_LO:
+    write16be(L, applyPPCLo(R));
+    break;
+  case R_PPC64_ADDR16_LO_DS:
+    write16be(L, (read16be(L) & 3) | (applyPPCLo(R) & ~3));
+    break;
+  case R_PPC64_ADDR16_HI:
+    write16be(L, applyPPCHi(R));
+    break;
+  case R_PPC64_ADDR16_HA:
+    write16be(L, applyPPCHa(R));
     break;
-  case R_PPC64_TOC:
-    // We don't create a TOC yet.
+  case R_PPC64_ADDR16_HIGHER:
+    write16be(L, applyPPCHigher(R));
+    break;
+  case R_PPC64_ADDR16_HIGHERA:
+    write16be(L, applyPPCHighera(R));
+    break;
+  case R_PPC64_ADDR16_HIGHEST:
+    write16be(L, applyPPCHighest(R));
+    break;
+  case R_PPC64_ADDR16_HIGHESTA:
+    write16be(L, applyPPCHighesta(R));
+    break;
+  case R_PPC64_ADDR14: {
+    if ((R & 3) != 0)
+      error("Improper alignment for relocation R_PPC64_ADDR14");
+
+    // Preserve the AA/LK bits in the branch instruction
+    uint8_t AALK = L[3];
+    write16be(L + 2, (AALK & 3) | (R & 0xfffc));
+    break;
+  }
+  case R_PPC64_REL16_LO:
+    write16be(L, applyPPCLo(R - P));
+    break;
+  case R_PPC64_REL16_HI:
+    write16be(L, applyPPCHi(R - P));
+    break;
+  case R_PPC64_REL16_HA:
+    write16be(L, applyPPCHa(R - P));
+    break;
+  case R_PPC64_ADDR32:
+    if (!isInt<32>(R))
+      error("Relocation R_PPC64_ADDR32 overflow");
+    write32be(L, R);
+    break;
+  case R_PPC64_REL24: {
+    uint32_t Mask = 0x03FFFFFC;
+    if (!isInt<24>(R - P))
+      error("Relocation R_PPC64_REL24 overflow");
+    write32be(L, (read32be(L) & ~Mask) | ((R - P) & Mask));
+    break;
+  }
+  case R_PPC64_REL32:
+    if (!isInt<32>(R - P))
+      error("Relocation R_PPC64_REL32 overflow");
+    write32be(L, R - P);
+    break;
+  case R_PPC64_REL64:
+    write64be(L, R - P);
+    break;
+  case R_PPC64_ADDR64:
+    write64be(L, R);
     break;
   default:
     error(Twine("unrecognized reloc ") + Twine(Type));
     break;
   }
 }
 
 PPCTargetInfo::PPCTargetInfo() {
   // PCRelReloc = FIXME
   // GotReloc = FIXME
   PageSize = 65536;
   VAStart = 0x10000000;
 }
 void PPCTargetInfo::writePltEntry(uint8_t *Buf, uint64_t GotEntryAddr,

test/elf2/ppc64-relocs.s

+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t
+# RUN: ld.lld2 %t -o %t2
+# RUN: llvm-objdump -d %t2 | FileCheck %s
+# REQUIRES: ppc
+
+.section        ".opd","aw"
+.global _start
+_start:
+.quad   .Lfoo,.TOC.@tocbase,0
+
+.text
+.Lfoo:
+  li      0,1
+  li      3,42
+  sc
+
+.section        ".toc","aw"
+.L1:
+.quad           22, 37, 89, 47
+
+.section .R_PPC64_TOC16_LO_DS,"ax",@progbits
+.globl .FR_PPC64_TOC16_LO_DS
+.FR_PPC64_TOC16_LO_DS:
+  ld 1, .L1@toc@l(2)
+
+# CHECK: Disassembly of section .R_PPC64_TOC16_LO_DS:
+# CHECK: .FR_PPC64_TOC16_LO_DS:
+# CHECK: 1001000c:       e8 22 80 00     ld 1, -32768(2)
+
+.section .R_PPC64_TOC16_LO,"ax",@progbits
+.globl .FR_PPC64_TOC16_LO
+.FR_PPC64_TOC16_LO:
+  addi  1, 2, .L1@toc@l
+
+# CHECK: Disassembly of section .R_PPC64_TOC16_LO:
+# CHECK: .FR_PPC64_TOC16_LO:
+# CHECK: 10010010: 38 22 80 00 addi 1, 2, -32768
+
+.section .R_PPC64_TOC16_HI,"ax",@progbits
+.globl .FR_PPC64_TOC16_HI
+.FR_PPC64_TOC16_HI:
+  addis 1, 2, .L1@toc@h
+
+# CHECK: Disassembly of section .R_PPC64_TOC16_HI:
+# CHECK: .FR_PPC64_TOC16_HI:
+# CHECK: 10010014: 3c 22 10 01 addis 1, 2, 4097
+
+.section .R_PPC64_TOC16_HA,"ax",@progbits
+.globl .FR_PPC64_TOC16_HA
+.FR_PPC64_TOC16_HA:
+  addis 1, 2, .L1@toc@ha
+
+# CHECK: Disassembly of section .R_PPC64_TOC16_HA:
+# CHECK: .FR_PPC64_TOC16_HA:
+# CHECK: 10010018: 3c 22 10 02 addis 1, 2, 4098
+
+.section .R_PPC64_REL24,"ax",@progbits
+.globl .FR_PPC64_REL24
+.FR_PPC64_REL24:
+  b .Lfoox
+.section .R_PPC64_REL24_2,"ax",@progbits
+.Lfoox:
+
+# CHECK: Disassembly of section .R_PPC64_REL24:
+# CHECK: .FR_PPC64_REL24:
+# CHECK: 1001001c: 48 00 00 04 b .+4
+
+.section .R_PPC64_ADDR16_LO,"ax",@progbits
+.globl .FR_PPC64_ADDR16_LO
+.FR_PPC64_ADDR16_LO:
+  li 1, .Lfoo@l
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_LO:
+# CHECK: .FR_PPC64_ADDR16_LO:
+# CHECK: 10010020: 38 20 00 00 li 1, 0
+
+.section .R_PPC64_ADDR16_HI,"ax",@progbits
+.globl .FR_PPC64_ADDR16_HI
+.FR_PPC64_ADDR16_HI:
+  li 1, .Lfoo@h
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_HI:
+# CHECK: .FR_PPC64_ADDR16_HI:
+# CHECK: 10010024: 38 20 10 01 li 1, 4097
+
+.section .R_PPC64_ADDR16_HA,"ax",@progbits
+.globl .FR_PPC64_ADDR16_HA
+.FR_PPC64_ADDR16_HA:
+  li 1, .Lfoo@ha
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_HA:
+# CHECK: .FR_PPC64_ADDR16_HA:
+# CHECK: 10010028: 38 20 10 01 li 1, 4097
+
+.section .R_PPC64_ADDR16_HIGHER,"ax",@progbits
+.globl .FR_PPC64_ADDR16_HIGHER
+.FR_PPC64_ADDR16_HIGHER:
+  li 1, .Lfoo@higher
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHER:
+# CHECK: .FR_PPC64_ADDR16_HIGHER:
+# CHECK: 1001002c: 38 20 00 00 li 1, 0
+
+.section .R_PPC64_ADDR16_HIGHERA,"ax",@progbits
+.globl .FR_PPC64_ADDR16_HIGHERA
+.FR_PPC64_ADDR16_HIGHERA:
+  li 1, .Lfoo@highera
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHERA:
+# CHECK: .FR_PPC64_ADDR16_HIGHERA:
+# CHECK: 10010030: 38 20 00 00 li 1, 0
+
+.section .R_PPC64_ADDR16_HIGHEST,"ax",@progbits
+.globl .FR_PPC64_ADDR16_HIGHEST
+.FR_PPC64_ADDR16_HIGHEST:
+  li 1, .Lfoo@highest
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHEST:
+# CHECK: .FR_PPC64_ADDR16_HIGHEST:
+# CHECK: 10010034: 38 20 00 00 li 1, 0
+
+.section .R_PPC64_ADDR16_HIGHESTA,"ax",@progbits
+.globl .FR_PPC64_ADDR16_HIGHESTA
+.FR_PPC64_ADDR16_HIGHESTA:
+  li 1, .Lfoo@highesta
+
+# CHECK: Disassembly of section .R_PPC64_ADDR16_HIGHESTA:
+# CHECK: .FR_PPC64_ADDR16_HIGHESTA:
+# CHECK: 10010038: 38 20 00 00 li 1, 0
+