[RISCV] Remove debug location to spill/reload instructions

[Miss_Grape]

Summary

The implementation of this patch is reference https://reviews.llvm.org/D52125

[kito-cheng]

Curious why remove that? for saving code size or it's inaccurate?

[• pcwang-thead]

In D129173#3631863, @kito-cheng wrote:

Curious why remove that? for saving code size or it's inaccurate?

Hmm, I think this patch is almost the same as D128806.

[Miss_Grape]

In D129173#3631894, @pcwang-thead wrote:

In D129173#3631863, @kito-cheng wrote:

Curious why remove that? for saving code size or it's inaccurate?

Hmm, I think this patch is almost the same as D128806.

Yes~

[kito-cheng]

I would suggest add more info into summary for this revision.

[Miss_Grape]

In D129173#3634461, @kito-cheng wrote:

I would suggest add more info into summary for this revision.

Move to D128806.

[benshi001]

My suggestion,

1. improve your commit info, something like

Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

Refered to https://reviews.llvm.org/rG3e081703c349dd00b8ef6991c2d15964915dd8f4

2. add some tests as you did in your another review request.

[Miss_Grape]

In D129173#4259845, @benshi001 wrote:

My suggestion,

1. improve your commit info, something like

Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

Refered to https://reviews.llvm.org/rG3e081703c349dd00b8ef6991c2d15964915dd8f4

2. add some tests as you did in your another review request.

Just remove the debugging information in the prologue of the function， neednt to add test cases

[benshi001]

I have referred to X86 and AArch64, they both use empty debug location information for spill/load instructions. I think it is OK for RISCV. But it would be better to improve your commit information as follow:

Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

Refered to https://reviews.llvm.org/rG3e081703c349dd00b8ef6991c2d15964915dd8f4

[kito-cheng]

LGTM, but please use @benshi001's suggestion in your git commit log

[asb]

LGTM, but please use a clear commit message as suggested by @benshi001. It also feels like this must be testable either with an MIR test or with llvm-dwarfdump.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 }
 
 void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator I,
                                          Register SrcReg, bool IsKill, int FI,
                                          const TargetRegisterClass *RC,
                                          const TargetRegisterInfo *TRI,
                                          Register VReg) const {
-  DebugLoc DL;
-  if (I != MBB.end())
-    DL = I->getDebugLoc();
-
   MachineFunction *MF = MBB.getParent();
   MachineFrameInfo &MFI = MF->getFrameInfo();
 
   unsigned Opcode;
   bool IsScalableVector = true;
   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::SW : RISCV::SD;
else
     llvm_unreachable("Can't store this register to stack slot");
 
   if (IsScalableVector) {
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
 
     MFI.setStackID(FI, TargetStackID::ScalableVector);
-    BuildMI(MBB, I, DL, get(Opcode))
+    BuildMI(MBB, I, DebugLoc(), get(Opcode))
         .addReg(SrcReg, getKillRegState(IsKill))
         .addFrameIndex(FI)
         .addMemOperand(MMO);
   } else {
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
-    BuildMI(MBB, I, DL, get(Opcode))
+    BuildMI(MBB, I, DebugLoc(), get(Opcode))
         .addReg(SrcReg, getKillRegState(IsKill))
         .addFrameIndex(FI)
         .addImm(0)
         .addMemOperand(MMO);
   }
 }
 
 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator I,
                                           Register DstReg, int FI,
                                           const TargetRegisterClass *RC,
                                           const TargetRegisterInfo *TRI,
                                           Register VReg) const {
-  DebugLoc DL;
-  if (I != MBB.end())
-    DL = I->getDebugLoc();
-
   MachineFunction *MF = MBB.getParent();
   MachineFrameInfo &MFI = MF->getFrameInfo();
 
   unsigned Opcode;
   bool IsScalableVector = true;
   if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::LW : RISCV::LD;
else
     llvm_unreachable("Can't load this register from stack slot");
 
   if (IsScalableVector) {
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
         MemoryLocation::UnknownSize, MFI.getObjectAlign(FI));
 
     MFI.setStackID(FI, TargetStackID::ScalableVector);
-    BuildMI(MBB, I, DL, get(Opcode), DstReg)
+    BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
         .addFrameIndex(FI)
         .addMemOperand(MMO);
   } else {
     MachineMemOperand *MMO = MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
         MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
-    BuildMI(MBB, I, DL, get(Opcode), DstReg)
+    BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
         .addFrameIndex(FI)
         .addImm(0)
         .addMemOperand(MMO);
   }
 }
 
 MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,