Let NVPTX backend detect integer min and max patterns during isel and emit intrinsics that enable hardware support.
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lib/Target/NVPTX/NVPTXISelLowering.cpp | ||
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4084 | These cases require some mental effort to reason about, although I struggled through them :) It might be better to do this: SDNode larger; // The larger operand when the condition is true. if (op is LT, LE, ULT, or ULE) { larger = RHS; } else { larger = LHS; } IsSigned = LT or LE or GT or GE; IsMax = (Larger == True); // IsMax iff the instruction returns the larger one when the condition is true. |
lib/Target/NVPTX/NVPTXISelLowering.cpp | ||
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4084 | I found isSignedIntSetCC which makes the logic simpler. I kept the switch, as I need to ensure that only these codes are used, not e.g. eq. |
If you make the generic min/max nodes legal, you don't need to do this pattern matching yourself
Thanks for the tip and, yes, using the generic min/max nodes would have been my preferred solution. However, I couldn't find documentation that clearly explained how tablegen for NVPTX exactly works and it seemed like I'd need to use tablegen to tell LLVM how to emit code from the generic min/max. Also, the generic code for detecting min/max patterns that I found was in DAGCombiner, which only works for floating point and not, as here, for integers, so I'd have to add that and ensure that I didn't mess up any other backend. DAGCombiner also requires hasOneUse() for the condition, which is not what I wanted here. The direct solution here was by comparison quite straightforward, so this time I decided to go for the easy solution.
These cases require some mental effort to reason about, although I struggled through them :)
It might be better to do this: