[CostModel][AArch64] Increase cost of vector insert element and add missing cast costs

[sbaranga]

Summary

Increase the estimated costs for insert/extract element operations on
AArch64. This is motivated by results from benchmarking interleaved
accesses.

Add missing costs for zext/sext/trunc instructions and some integer to
floating point conversions. These costs were previously calculated
by scalarizing these operation and were affected by the cost increase of
the insert/extract element operations.

[sbaranga]

Benchmarking results (lnt, spec2000, spec2006) on cortex-a53/cortex-a57 at r243774

Cortex-A53:

Regressions:
lnt.MultiSource/Benchmarks/Prolangs-C++/primes/primes 2.97%
lnt.MultiSource/Benchmarks/TSVC/LinearDependence-flt/LinearDependence-flt 1.39%
spec.cpu2006.ref.464_h264ref 1.09%

Performance Improvements - Execution Time
lnt.MultiSource/Benchmarks/Trimaran/enc-pc1/enc-pc1 -21.93%
lnt.SingleSource/Benchmarks/BenchmarkGame/puzzle -16.42%
lnt.MultiSource/Benchmarks/TSVC/GlobalDataFlow-flt/GlobalDataFlow-flt -5.00%
lnt.SingleSource/Benchmarks/Misc/flops -3.16%
spec.cpu2000.ref.183_equake -2.54%
lnt.MultiSource/Benchmarks/ASC_Sequoia/IRSmk/IRSmk -1.97%
spec.cpu2000.ref.253_perlbmk -1.18%
spec.cpu2006.ref.447_dealII -1.10%

Cortex-A57:

Performance Regressions - Execution Time
lnt.MultiSource/Benchmarks/BitBench/five11/five11 3.20%
spec.cpu2006.ref.482_sphinx3 1.27%
lnt.SingleSource/Benchmarks/BenchmarkGame/n-body 1.03%

Performance Improvements - Execution Time
lnt.SingleSource/Benchmarks/BenchmarkGame/puzzle -16.11%
lnt.MultiSource/Benchmarks/Olden/bh/bh -8.30%
lnt.MultiSource/Benchmarks/Trimaran/enc-pc1/enc-pc1 -5.39%
lnt.MultiSource/Benchmarks/TSVC/GlobalDataFlow-flt/GlobalDataFlow-flt -4.37%
lnt.MultiSource/Applications/hexxagon/hexxagon -4.14%
lnt.SingleSource/UnitTests/Vectorizer/gcc-loops -4.06%
lnt.MultiSource/Benchmarks/TSVC/ControlFlow-flt/ControlFlow-flt -2.55%
spec.cpu2006.ref.453_povray -2.31%
spec.cpu2006.ref.444_namd -2.16%
lnt.SingleSource/Benchmarks/Misc-C++/oopack_v1p8 -1.80%
lnt.SingleSource/Benchmarks/Shootout-C++/methcall -1.23%
lnt.MultiSource/Benchmarks/TSVC/ControlLoops-flt/ControlLoops-flt -1.14%
lnt.SingleSource/Benchmarks/Shootout-C++/ary3 -1.00%

[rengolin]

The changes make sense to what we've seen so far about the shuffles, and the benchmark numbers are very compelling.

Thanks for computing that table!

LGTM. Thanks!

[sbaranga]

Thanks, Renato! I'll commit this on Monday

Cheers,
Silviu

[sbaranga]

Thanks, r245226

-Silviu

lib/Target/AArch64/AArch64TargetTransformInfo.cpp

int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
 
   EVT SrcTy = TLI->getValueType(DL, Src);
   EVT DstTy = TLI->getValueType(DL, Dst);
 
   if (!SrcTy.isSimple() || !DstTy.isSimple())
     return BaseT::getCastInstrCost(Opcode, Dst, Src);
 
   static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = {
+    { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
+    { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
+    { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
+    { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
+    { ISD::TRUNCATE,    MVT::v4i32, MVT::v4i64, 0 },
+    { ISD::TRUNCATE,    MVT::v4i16, MVT::v4i32, 1 },
+
+    // The number of shll instructions for the extension.
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
+    { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
+    { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
+    { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
+    { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
+    { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
+    { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
+    { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
+    { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
+
+    { ISD::TRUNCATE,    MVT::v16i8, MVT::v16i32, 6 },
+    { ISD::TRUNCATE,    MVT::v8i8, MVT::v8i32, 3 },
+
     // LowerVectorINT_TO_FP:
     { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
     { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
 
     // Complex: to v2f32
     { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8,  3 },
     { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
     { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
     { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8,  3 },
     { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
     { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
 
     // Complex: to v4f32
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8,  4 },
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8,  3 },
     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
 
+    // Complex: to v8f32
+    { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8,  10 },
+    { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
+    { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8,  10 },
+    { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
+
+    // Complex: to v16f32
+    { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
+    { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
+
     // Complex: to v2f64
     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8,  4 },
     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8,  4 },
     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
 
if (Index != -1U) {
     Index = Index % Width;
 
     // The element at index zero is already inside the vector.
     if (Index == 0)
       return 0;
   }
 
   // All other insert/extracts cost this much.
-  return 2;
+  return 3;
 }
 
 int AArch64TTIImpl::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
     TTI::OperandValueProperties Opd2PropInfo) {
   // Legalize the type.
   std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);

test/Transforms/SLPVectorizer/AArch64/commute.ll

-; RUN: opt -S -slp-vectorizer %s | FileCheck %s
+; RUN: opt -S -slp-vectorizer %s -slp-threshold=-10 | FileCheck %s
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-gnu"
 
 %structA = type { [2 x float] }
 
 define void @test1(%structA* nocapture readonly %J, i32 %xmin, i32 %ymin) {
 ; CHECK-LABEL: test1
 ; CHECK: %arrayidx4 = getelementptr inbounds %structA, %structA* %J, i64 0, i32 0, i64 0