Fix Hexagon optimize addressing mode pass so that it handles only BaseImmOffset addressing mode.

[pranavb]

Summary

This is a fix for a crash in the HexagonOptAddrMode pass that was looking for the third operand (offset) in the following instruction
that does not, in fact, have a third operand.

$r1 = L2_loadw_locked $r1

Additionally, this patch also adds an addrMode value to vgather pseudos in the Hexagon backend.

[pranavb]

Formatted using clang-format.

[pranavb]

Fixed run line in testcase

[srj]

Any ETA on when this will land?

[pranavb]

Let me ping Krzysztof and Sumanth for a review of the latest revision. This is ready to land as far as I am concerned.

llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp

unsigned HexagonOptAddrMode::getBaseOpPosition(MachineInstr *MI) {
   case Hexagon::V6_vgathermhwq_pseudo:
     return 0;
   default:
     return MID.mayLoad() ? 1 : 0;
   }
 }
 
 unsigned HexagonOptAddrMode::getOffsetOpPosition(MachineInstr *MI) {
+  assert(
+      (HII->getAddrMode(*MI) == HexagonII::BaseImmOffset) &&
+      "Looking for an offset in non-BaseImmOffset addressing mode instruction");
+
   const MCInstrDesc &MID = MI->getDesc();
   switch (MI->getOpcode()) {
   // vgather pseudos are mayLoad and mayStore
   // hence need to explicitly specify Base and
   // Offset operand positions
   case Hexagon::V6_vgathermh_pseudo:
   case Hexagon::V6_vgathermw_pseudo:
   case Hexagon::V6_vgathermhw_pseudo:
bool HexagonOptAddrMode::processAddUses(NodeAddr<StmtNode *> AddSN,
 
   Register AddDefR = AddMI->getOperand(0).getReg();
   Register BaseReg = AddMI->getOperand(1).getReg();
   for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
     NodeAddr<UseNode *> UN = *I;
     NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
     MachineInstr *MI = SN.Addr->getCode();
     const MCInstrDesc &MID = MI->getDesc();
-    if ((!MID.mayLoad() && !MID.mayStore()))
-        return false;
+    if ((!MID.mayLoad() && !MID.mayStore()) ||
+        HII->getAddrMode(*MI) != HexagonII::BaseImmOffset)
 
     MachineOperand BaseOp = MI->getOperand(getBaseOpPosition(MI));
 
     if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
       return false;
 
     MachineOperand OffsetOp = MI->getOperand(getOffsetOpPosition(MI));
     if (!OffsetOp.isImm())

llvm/lib/Target/Hexagon/HexagonPatternsV65.td

 //==- HexagonPatternsV65.td -------------------------------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 multiclass vgathermh<RegisterClass RC> {
-  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
+  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
   def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                            (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
                            ".error \"should not emit\" ",
                            []>;
 }
 
 multiclass vgathermw<RegisterClass RC> {
-  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
+  mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
   def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                            (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
                            ".error \"should not emit\" ",
                            []>;
 }
 
 multiclass vgathermhw<RegisterClass RC> {
-  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
+   mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
   def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                            (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
                            ".error \"should not emit\" ",
                            []>;
 }
 
 defm V6_vgathermh_pseudo  : vgathermh<HvxVR>;
 defm V6_vgathermw_pseudo  : vgathermw<HvxVR>;
 defm V6_vgathermhw_pseudo  : vgathermhw<HvxWR>;
 
 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
-  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
+  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
   def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                            (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
                                 RC1:$Vv),
                            ".error \"should not emit\" ",
                            []>;
 }
 
 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
-  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
+  mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
   def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                            (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
                                 RC1:$Vv),
                            ".error \"should not emit\" ",
                            []>;
 }
 
 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
-  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
+  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
+  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess  in
   def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                            (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                               RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
                               RC1:$Vv),
                            ".error \"should not emit\" ",
                            []>;
 }
 
 defm V6_vgathermhq_pseudo  : vgathermhq<HvxVR, HvxQR>;
 defm V6_vgathermwq_pseudo  : vgathermwq<HvxVR, HvxQR>;
 defm V6_vgathermhwq_pseudo  : vgathermhwq<HvxWR, HvxQR>;

llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir

+# RUN: llc -march=hexagon -mcpu=hexagonv62  -run-pass amode-opt %s -o -
+# REQUIRES: asserts
+#
+# This test merely checks if the pass that optimizes addressing modes in the
+# hexagon backend doesn't crash when the following code is presented to it.
+#
+# This is a testcase reduced from code generated by the Halide compiler for a
+# Halide pipeline. This code was causing the pass 'amode-opt' to crash because
+# it was looking for the third operand (offset) in the following instruction
+# that does not, in fact, have a third operand.
+#
+#          $r1 = L2_loadw_locked $r1
+#
+# Check that this doesn't crash.
+
+
+name: fred
+tracksRegLiveness: true
+body: |
+   bb.0:
+   liveins: $r0
+   $r1 = A2_addi $r0, 4
+   $r1 = L2_loadw_locked $r1
+...