This requires a fix in tablegen for the cast<int> from bits<16> to work in the list initializer.
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lib/Target/AMDGPU/SIRegisterInfo.td | ||
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13–14 | Is it OK for vgprs and sgprs to have the same DwarfRegNum? |
lib/Target/AMDGPU/SIRegisterInfo.td | ||
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13–14 | I assume not. This isn't what's happening though. I originally was setting this from the encoding parameter to SIReg, but this was getting the same value for SGPRs and VGPRs, so I so I renamed it to regIdx and set it from HWEncoding because the VGPRs set HWEncoding{8} separately (although for the special registers regIdx isn't really an accurate name) |
Is it OK for vgprs and sgprs to have the same DwarfRegNum?