Add support for nest attribute to ARM backend

[• scross99]

Summary

The nest attribute is currently supported on the x86 (32-bit), x86-64, PowerPC and AArch64 backends, but not on ARM (32-bit). This patch adds support for nest to the ARM backend.

Register r12 ('ip') is used by GCC for this purpose (see https://github.com/gcc-mirror/gcc/blob/7c62dfbbcd3699efcbbadc9fb3aa14f23a123add/gcc/testsuite/gcc.dg/cwsc1.c ) and hence is used here. As discussed on the GCC mailing list (see http://www.mail-archive.com/[e-mail]/msg76966.html ) the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible.

Relevant LLVM mailing list discussion: http://comments.gmane.org/gmane.comp.compilers.llvm.devel/86370

[rengolin]

As similar to AArch64, this patch looks good to me.

Committed as r241996.

cheers,
--renato

lib/Target/ARM/ARMCallingConv.td

 //===----------------------------------------------------------------------===//
 // ARM AAPCS (EABI) Calling Convention
 //===----------------------------------------------------------------------===//
 
 def CC_ARM_AAPCS : CallingConv<[
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
+  // The 'nest' parameter, if any, is passed in R12.
+  CCIfNest<CCAssignToReg<[R12]>>,
+
   // Handle all vector types as either f64 or v2f64.
   CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
   CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
 
   CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
   CCIfType<[f32], CCBitConvertToType<i32>>,
   CCDelegateTo<CC_ARM_AAPCS_Common>
 ]>;

test/CodeGen/ARM/nest-register.ll

+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+
+; Tests that the 'nest' parameter attribute causes the relevant parameter to be
+; passed in the right register.
+
+define i8* @nest_receiver(i8* nest %arg) nounwind {
+; CHECK-LABEL: nest_receiver:
+; CHECK: @ BB#0:
+; CHECK-NEXT: mov r0, r12
+; CHECK-NEXT: mov pc, lr
+        ret i8* %arg
+}
+
+define i8* @nest_caller(i8* %arg) nounwind {
+; CHECK-LABEL: nest_caller:
+; CHECK: mov r12, r0
+; CHECK-NEXT: bl nest_receiver
+; CHECK: mov pc, lr
+        %result = call i8* @nest_receiver(i8* nest %arg)
+        ret i8* %result
+}