[ARM] Don't be overzealous converting Thumb1 3 to 2 operands

[scott-0]

Summary

Small shifts can be done in 3 operand form and the ARMARM says they should not be converted to 2 operand.

Depends on http://reviews.llvm.org/D11054.

[rengolin]

What about the FIXME that you had added in the tests earlier on? Didn't that get fixed?

[scott-0]

This one?
@ FIXME: ARMARM says 'add sp, sp, #32'
@ CHECK: add sp, #32 @ encoding: [0x08,0xb0]

No, I haven't fixed that yet (in any patch).

This patch is just implementing "Encoding T1 is preferred to encoding T2 if <Rd> is specified and encoding T2 is preferred to encoding T1 if <Rd> is omitted." (ARMARM v7-A/R rev C.c page A8-307)

[rengolin]

Right, ok. Thanks!

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
   // If both registers are the same then remove one of them from
   // the operand list, with certain exceptions.
   if (Transform) {
     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
     // 2 operand forms don't exist.
     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
         Op5.isReg())
       Transform = false;
+
+    // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
+    // 3-bits because the ARMARM says not to.
+    if ((Mnemonic == "add" || Mnemonic == "sub") && Op5.isImm0_7())
+      Transform = false;
   }
 
   if (Transform)
     Operands.erase(Operands.begin() + 3);
 }
 
 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
                                           OperandVector &Operands) {

llvm/trunk/test/MC/ARM/thumb_rewrites.s

 @ RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s
 
+    adds    r1, r1, #3
+@ CHECK: adds   r1, r1, #3          @ encoding: [0xc9,0x1c]
+
+    adds    r1, #3
+@ CHECK: adds   r1, #3              @ encoding: [0x03,0x31]
+
     adds    r0, r0, #8
 @ CHECK: adds   r0, #8              @ encoding: [0x08,0x30]
 
     adds    r0, r0, r0
 @ CHECK: adds   r0, r0, r0          @ encoding: [0x00,0x18]
 
     add     r0, r0, r8
 @ CHECK: add    r0, r8              @ encoding: [0x40,0x44]

 @ CHECK: add    r0, r1              @ encoding: [0x08,0x44]
 
     add     r2, r2, r3
 @ CHECK: add    r2, r3              @ encoding: [0x1a,0x44]
 
     subs    r0, r0, r0
 @ CHECK: subs   r0, r0, r0          @ encoding: [0x00,0x1a]
 
+    subs    r3, r3, #5
+@ CHECK: subs   r3, r3, #5          @ encoding: [0x5b,0x1f]
+
+    subs    r3, #5
+@ CHECK: subs   r3, #5              @ encoding: [0x05,0x3b]
+
     subs    r2, r2, #8
 @ CHECK: subs   r2, #8              @ encoding: [0x08,0x3a]
 
     sub     sp, sp, #16
 @ CHECK: sub    sp, #16             @ encoding: [0x84,0xb0]
 
     ands    r0, r0, r1
 @ CHECK: ands   r0, r1              @ encoding: [0x08,0x40]