Add missing builtins to the PPC back end for ABI compliance (vol. 3)

[nemanjai]

Summary

This patch corresponds to review:
http://reviews.llvm.org/D10972

Back end portion of the third round of additions to altivec.h.

[hfinkel]

lib/Target/PowerPC/PPCInstrVSX.td

1175

Please put this pattern with the other similar ones (around like 1000 it seems).

[wschmidt]

No further comments from me.

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

1175

I can put it closer to those, but this one needs the definition of XXLEQV and requires HasP8Vector.

[nemanjai]

@hfinkel Hal, could you please comment as to where you would like me to put the pattern. With the other ones (around line 1000) isn't really an option since it would be before the definition of the instruction that it uses. I can move ALL the patern fragments into one section below the definition of the instructions (keeping the correct predicates with each group).
If you actually don't want me to move it, can you please approve the changeset?
@wschmidt Bill, I can't commit D10972 without committing this. I'll get both of them in once this one is approved.

[hfinkel]

lib/Target/PowerPC/PPCInstrVSX.td

1175

We should talk about how to best organize these files, because the scheme that existed previously has now been disrupted somewhat (not obviously in a bad way, but different from what we had before).

Please just move this to after where XXLEQV and XXLNAND are defined for now.

LGTM.

[nemanjai]

Committed revision 241900.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xvcmpgesp :
       PowerPC_VSX_Intrinsic<"xvcmpgesp", [llvm_v4i32_ty],
                             [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvcmpgtdp :
       PowerPC_VSX_Intrinsic<"xvcmpgtdp", [llvm_v2i64_ty],
                             [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvcmpgtsp :
       PowerPC_VSX_Intrinsic<"xvcmpgtsp", [llvm_v4i32_ty],
                             [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xxleqv :
+      PowerPC_VSX_Intrinsic<"xxleqv", [llvm_v4i32_ty],
+                            [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
   let IsVSXFMAAlt = 1 in
   def XSNMSUBMSP : XX3Form<60, 153,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
+  def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
+            (XXLEQV $A, $B)>;
 } // AddedComplexity = 400
 } // HasP8Vector
 
 let Predicates = [HasDirectMove, HasVSX] in {
   // VSX direct move instructions
   def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
                               "mfvsrd $rA, $XT", IIC_VecGeneral,
                               [(set i64:$rA, (PPCmfvsr f64:$XT))]>,