[CodeGen] Don't crash classifying a union of an AVX vector and an int

[majnemer]

Summary

We forgot to run postMerge after decided that the union had to be
classified as MEMORY. This left us with Lo == MEMORY and Hi == SSEUp
which is an invalid combination.

This fixes PR24021.

[Sunil_Srivastava]

This change fixes the assertion failure in my full test case of several hundred combinations.

[rjmccall]

LGTM.

cfe/trunk/lib/CodeGen/TargetInfo.cpp

for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
       // four eightbytes, or it contains unaligned fields, it has class MEMORY.
       //
       // The only case a 256-bit wide vector could be used is when the struct
       // contains a single 256-bit element. Since Lo and Hi logic isn't extended
       // to work for sizes wider than 128, early check and fallback to memory.
       //
       if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) {
         Lo = Memory;
+        postMerge(Size, Lo, Hi);
         return;
       }
       // Note, skip this test for bit-fields, see below.
       if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
         Lo = Memory;
+        postMerge(Size, Lo, Hi);
         return;
       }
 
       // Classify this field.
       //
       // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
       // exceeds a single eightbyte, each is classified
       // separately. Each eightbyte gets initialized to class

cfe/trunk/test/CodeGenCXX/x86_64-arguments-avx.cpp

union UU2 {
   __m256d v3;
 };
 
 // CHECK: define <4 x double> @_ZN5test27PR23082ENS_3UU2E(<4 x double>
 UU2 PR23082(UU2 x) {
   return x;
 }
 }
+
+namespace test3 {
+union U {
+  __attribute__((__vector_size__(32))) float f1;
+  int f2;
+};
+// CHECK: define i32 @_ZN5test31fENS_1UE({{.*}}* byval align 32
+int f(U u) { return u.f2; }
+}