Add missing builtins to the PPC back end for ABI compliance (vol. 2)

[nemanjai]

Summary

Back end portion of the second round of additions to altivec.h.

[wschmidt]

LGTM.

[echristo]

One inline comment and then LGTM.

-eric

test/CodeGen/PowerPC/vsx-elementary-arith.ll

121–136

Hrm. I'd suggest running this through the optimizer but since it's just using locals that don't have external visibility it might not work. Though if the instruction selector ever does any DCE on allocas then there's going to be a problem here. Might want to have it take arguments and return something?

[nemanjai]

test/CodeGen/PowerPC/vsx-elementary-arith.ll

121–136

OK, I'll split this up into two functions that return the result of the call to the builtin. Please let me know if you agree with that approach.

[echristo]

Sure. Sounds good.

-eric

[nemanjai]

Committed revision 241398.

include/llvm/IR/IntrinsicsPowerPC.td

 def int_ppc_vsx_xvdivsp : PowerPC_VSX_Vec_FFF_Intrinsic<"xvdivsp">;
 
 // Vector round-to-infinity (ceil)
 def int_ppc_vsx_xvrspip :
       Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvrdpip :
       Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
 
+// Vector rsqrte
+def int_ppc_vsx_xvrsqrtesp : GCCBuiltin<"__builtin_vsx_xvrsqrtesp">,
+      Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvrsqrtedp : GCCBuiltin<"__builtin_vsx_xvrsqrtedp">,
+      Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
+
 // Vector compare
 def int_ppc_vsx_xvcmpeqdp :
       PowerPC_VSX_Intrinsic<"xvcmpeqdp", [llvm_v2i64_ty],
                             [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvcmpeqsp :
       PowerPC_VSX_Intrinsic<"xvcmpeqsp", [llvm_v4i32_ty],
                             [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvcmpgedp :

lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
           (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>;
 
 // Divides.
 def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
           (XVDIVSP $A, $B)>;
 def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
           (XVDIVDP $A, $B)>;
 
+// Recip. square root estimate
+def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A),
+          (XVRSQRTESP $A)>;
+def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A),
+          (XVRSQRTEDP $A)>;
+
 } // AddedComplexity
 } // HasVSX
 
 // The following VSX instructions were introduced in Power ISA 2.07
 /* FIXME: if the operands are v2i64, these patterns will not match.
    we should define new patterns or otherwise match the same patterns
    when the elements are larger than i32.
 */

test/CodeGen/PowerPC/vsx-elementary-arith.ll

 entry:
   %0 = load double, double* @d, align 8
   %call = call double @sqrt(double %0)
   ret double %call
 ; CHECK-LABEL: @emit_xssqrtdp
 ; CHECK: xssqrtdp {{[0-9]+}}
 }
 
+; Vector forms
+; Function Attrs: nounwind
+define void @emit_xvrsqrte() #0 {
+entry:
+; CHECK-LABEL: @emit_xvrsqrte
+  %vf = alloca <4 x float>, align 16
+  %vfr = alloca <4 x float>, align 16
+  %vd = alloca <2 x double>, align 16
+  %vdr = alloca <2 x double>, align 16
+  %0 = load <4 x float>, <4 x float>* %vf, align 16
+  %1 = call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %0)
+; CHECK: xvrsqrtesp {{[0-9]+}}, {{[0-9]+}}
+  store <4 x float> %1, <4 x float>* %vfr, align 16
+  %2 = load <2 x double>, <2 x double>* %vd, align 16
+  %3 = call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %2)
+; CHECK: xvrsqrtedp {{[0-9]+}}, {{[0-9]+}}
+  store <2 x double> %3, <2 x double>* %vdr, align 16
+  ret void
+}
+
 ; Function Attrs: nounwind
 declare double @sqrt(double)
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float>)
+
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double>)