[SPARC] Fix BooleanContents, so that select of a trunc doesn't eliminate the trunc.

[jyknight]

ping.

[jyknight]

ping.

[echristo]

LGTM.
-eric

[jyknight]

Was closed by commit r245444.

lib/Target/Sparc/SparcISelLowering.cpp

static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
   case ISD::SETONE: return SPCC::FCC_LG;
   case ISD::SETUEQ: return SPCC::FCC_UE;
   }
 }
 
 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
                                          const SparcSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
+
+  // Instruction which use registers as conditionals examine all the
+  // bits (as does the pseudo SELECT_CC expansion). I don't think it
+  // matters much whether it's ZeroOrOneBooleanContent, or
+  // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
+  // former.
+  setBooleanContents(ZeroOrOneBooleanContent);
+  setBooleanVectorContents(ZeroOrOneBooleanContent);
+
   // Set up the register classes.
   addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
   addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
   addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
   addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
   if (Subtarget->is64Bit())
     addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
 

test/CodeGen/SPARC/select-mask.ll

+; RUN: llc -march=sparc < %s
+
+;; getBooleanContents on Sparc used to claim that no bits mattered
+;; other than the first for SELECT. Thus, the 'trunc' got eliminated
+;; as redundant. But, cmp does NOT ignore the other bits!
+
+; CHECK-LABEL select_mask:
+; CHECK: ldub [%o0], [[R:%[goli][0-7]]]
+; CHECK: and [[R]], 1, [[V:%[goli][0-7]]]
+; CHECK: cmp [[V]], 0
+define i32 @select_mask(i8* %this) {
+entry:
+  %bf.load2 = load i8, i8* %this, align 4
+  %bf.cast5 = trunc i8 %bf.load2 to i1
+  %cond = select i1 %bf.cast5, i32 2, i32 0
+  ret i32 %cond
+}