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Differential D10769

[ARM] Cortex-R5 is not VFPOnlySP
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Authored by javed.absar on Jun 26 2015, 10:06 AM.

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rGbced3032e02b: [ARM] Cortex-R5 is not VFPOnlySP
rL240799: [ARM] Cortex-R5 is not VFPOnlySP

Summary

The model in ARM.td describes cortex-r5 as "FeatureVFPOnlySP". This is incorrect as Cortex-R5 TRM Sec 11.1.1 , states "FPU fully supports single-precision and double-precision add, subtract.."

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Repository: rL LLVM

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javed.absar updated this revision to Diff 28570.Jun 26 2015, 10:06 AM

javed.absar retitled this revision from to [ARM] Cortex-R5 is not VFPOnlySP.

javed.absar updated this object.

javed.absar edited the test plan for this revision. (Show Details)

javed.absar set the repository for this revision to rL LLVM.

javed.absar added a subscriber: Unknown Object (MLST).

Herald added subscribers: aemerson, rengolin. · View Herald TranscriptJun 26 2015, 10:06 AM

LGTM.

This revision is now accepted and ready to land.Jun 26 2015, 10:10 AM

Closed by commit rL240799: [ARM] Cortex-R5 is not VFPOnlySP (authored by javed.absar). · Explain WhyJun 26 2015, 10:42 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

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llvm/

trunk/

lib/

Target/

ARM/

2 lines

test/

CodeGen/

ARM/

build-attributes.ll

2 lines

Diff 28577

llvm/trunk/lib/Target/ARM/ARM.td

	Show First 20 Lines • Show All 410 Lines • ▼ Show 20 Lines		def : ProcessorModel<"cortex-r4f", CortexA8Model,
	[ProcR4,			[ProcR4,
	FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,			FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
	FeatureVFP3, FeatureD16]>;			FeatureVFP3, FeatureD16]>;

	// FIXME: R5 has currently the same ProcessorModel as A8.			// FIXME: R5 has currently the same ProcessorModel as A8.
	def : ProcessorModel<"cortex-r5", CortexA8Model,			def : ProcessorModel<"cortex-r5", CortexA8Model,
	[ProcR5, HasV7Ops, FeatureDB,			[ProcR5, HasV7Ops, FeatureDB,
	FeatureVFP3, FeatureDSPThumb2,			FeatureVFP3, FeatureDSPThumb2,
	FeatureHasRAS, FeatureVFPOnlySP,			FeatureHasRAS,
	FeatureD16, FeatureRClass]>;			FeatureD16, FeatureRClass]>;

	// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.			// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
	def : ProcessorModel<"cortex-r7", CortexA8Model,			def : ProcessorModel<"cortex-r7", CortexA8Model,
	[ProcR5, HasV7Ops, FeatureDB,			[ProcR5, HasV7Ops, FeatureDB,
	FeatureVFP3, FeatureDSPThumb2,			FeatureVFP3, FeatureDSPThumb2,
	FeatureHasRAS, FeatureVFPOnlySP,			FeatureHasRAS, FeatureVFPOnlySP,
	FeatureD16, FeatureMP, FeatureRClass]>;			FeatureD16, FeatureMP, FeatureRClass]>;
	▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/ARM/build-attributes.ll

	Show First 20 Lines • Show All 1,065 Lines • ▼ Show 20 Lines
	; CORTEX-R5-NOT: .eabi_attribute 19			; CORTEX-R5-NOT: .eabi_attribute 19
	;; We default to IEEE 754 compliance			;; We default to IEEE 754 compliance
	; CORTEX-R5: .eabi_attribute 20, 1			; CORTEX-R5: .eabi_attribute 20, 1
	; CORTEX-R5: .eabi_attribute 21, 1			; CORTEX-R5: .eabi_attribute 21, 1
	; CORTEX-R5-NOT: .eabi_attribute 22			; CORTEX-R5-NOT: .eabi_attribute 22
	; CORTEX-R5: .eabi_attribute 23, 3			; CORTEX-R5: .eabi_attribute 23, 3
	; CORTEX-R5: .eabi_attribute 24, 1			; CORTEX-R5: .eabi_attribute 24, 1
	; CORTEX-R5: .eabi_attribute 25, 1			; CORTEX-R5: .eabi_attribute 25, 1
	; CORTEX-R5: .eabi_attribute 27, 1			; CORTEX-R5-NOT: .eabi_attribute 27, 1
	; CORTEX-R5-NOT: .eabi_attribute 28			; CORTEX-R5-NOT: .eabi_attribute 28
	; CORTEX-R5-NOT: .eabi_attribute 36			; CORTEX-R5-NOT: .eabi_attribute 36
	; CORTEX-R5: .eabi_attribute 38, 1			; CORTEX-R5: .eabi_attribute 38, 1
	; CORTEX-R5-NOT: .eabi_attribute 42			; CORTEX-R5-NOT: .eabi_attribute 42
	; CORTEX-R5: .eabi_attribute 44, 2			; CORTEX-R5: .eabi_attribute 44, 2
	; CORTEX-R5-NOT: .eabi_attribute 68			; CORTEX-R5-NOT: .eabi_attribute 68

	; CORTEX-R5-FAST-NOT: .eabi_attribute 19			; CORTEX-R5-FAST-NOT: .eabi_attribute 19
	▲ Show 20 Lines • Show All 165 Lines • Show Last 20 Lines