MIR Serialization: Serialize the implicit register flags.

[arphaman]

Summary

This patch is based on a previous serialization patch that serializes register mask machine operands (http://reviews.llvm.org/D10673).

This patch serializes the implicit register flag. This patch introduces two new keywords into the
machine instruction syntax: 'implicit' and 'implicit-def'. The 'implicit' keyword is used for the implicit
register operands, and the 'implicit-def' keyword is used for the register operands that have the
implicit and define flag. Examples:

CMP32ri8 %edi, 10, implicit-def %eflags
JG_1 %bb.2.exit, implicit %eflags

This patch also adds a way to control the implicit machine operands - if a parser encounters a
register operand with an 'implicit' or 'implicit-def' flag, it will assume that this instruction specifies
all the implicit operands explicitly. But if the parser encounters an instruction that has no implicit register
operands, it will add the implicit register operands that are specified by the instruction information.
This means that the instruction:

CMP32ri8 %edi, 10

Is equivalent to:

CMP32ri8 %edi, 10, implicit-def %eflags

[arphaman]

The updated patch now follows a more conservative approach, where the machine instruction parser doesn't add the implicit register operands to instructions that don't specify any implicit operands.

[arphaman]

I rebased this patch on top of trunk.

llvm/trunk/lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     Eof,
     Error,
 
     // Tokens with no info.
     comma,
     equal,
     underscore,
 
+    // Keywords
+    kw_implicit,
+    kw_implicit_define,
+
     // Identifier tokens
     Identifier,
     NamedRegister,
     MachineBasicBlock,
     NamedGlobalValue,
     GlobalValue,
 
     // Other tokens
public:
   TokenKind kind() const { return Kind; }
 
   bool isError() const { return Kind == Error; }
 
   bool isRegister() const {
     return Kind == NamedRegister || Kind == underscore;
   }
 
+  bool isRegisterFlag() const {
+    return Kind == kw_implicit || Kind == kw_implicit_define;
+  }
+
   bool is(TokenKind K) const { return Kind == K; }
 
   bool isNot(TokenKind K) const { return Kind != K; }
 
   StringRef::iterator location() const { return Range.begin(); }
 
   StringRef stringValue() const { return Range.drop_front(StringOffset); }
 

llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp

 //===- MILexer.cpp - Machine instructions lexer implementation ----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the lexing of machine instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MILexer.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include <cctype>
 
 using namespace llvm;
 
 namespace {
 
 /// This class provides a way to iterate and get characters from the source
while (isspace(C.peek()))
     C.advance();
   return C;
 }
 
 static bool isIdentifierChar(char C) {
   return isalpha(C) || isdigit(C) || C == '_' || C == '-' || C == '.';
 }
 
+static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
+  return StringSwitch<MIToken::TokenKind>(Identifier)
+      .Case("_", MIToken::underscore)
+      .Case("implicit", MIToken::kw_implicit)
+      .Case("implicit-def", MIToken::kw_implicit_define)
+      .Default(MIToken::Identifier);
+}
+
 static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
   if (!isalpha(C.peek()) && C.peek() != '_')
     return None;
   auto Range = C;
   while (isIdentifierChar(C.peek()))
     C.advance();
   auto Identifier = Range.upto(C);
-  Token = MIToken(Identifier == "_" ? MIToken::underscore : MIToken::Identifier,
-                  Identifier);
+  Token = MIToken(getIdentifierKind(Identifier), Identifier);
   return C;
 }
 
 static Cursor maybeLexMachineBasicBlock(
     Cursor C, MIToken &Token,
     function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {
   if (!C.remaining().startswith("%bb."))
     return None;

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

 
 #include "MIParser.h"
 #include "MILexer.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/AsmParser/SlotMapping.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
 using namespace llvm;
 
public:
   ///
   /// This function always return true.
   bool error(StringRef::iterator Loc, const Twine &Msg);
 
   bool parse(MachineInstr *&MI);
   bool parseMBB(MachineBasicBlock *&MBB);
 
   bool parseRegister(unsigned &Reg);
+  bool parseRegisterFlag(unsigned &Flags);
   bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
   bool parseImmediateOperand(MachineOperand &Dest);
   bool parseMBBReference(MachineBasicBlock *&MBB);
   bool parseMBBOperand(MachineOperand &Dest);
   bool parseGlobalAddressOperand(MachineOperand &Dest);
   bool parseMachineOperand(MachineOperand &Dest);
 
 private:

 
 bool MIParser::parse(MachineInstr *&MI) {
   lex();
 
   // Parse any register operands before '='
   // TODO: Allow parsing of multiple operands before '='
   MachineOperand MO = MachineOperand::CreateImm(0);
   SmallVector<MachineOperand, 8> Operands;
-  if (Token.isRegister()) {
+  if (Token.isRegister() || Token.isRegisterFlag()) {
     if (parseRegisterOperand(MO, /*IsDef=*/true))
       return true;
     Operands.push_back(MO);
     if (Token.isNot(MIToken::equal))
       return error("expected '='");
     lex();
   }
 
if (Token.is(MIToken::Eof))
       break;
     if (Token.isNot(MIToken::comma))
       return error("expected ',' before the next machine operand");
     lex();
   }
 
   const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
 
-  // Verify machine operands.
-  if (!MCID.isVariadic()) {
-    for (size_t I = 0, E = Operands.size(); I < E; ++I) {
-      if (I < MCID.getNumOperands())
-        continue;
-      // Mark this register as implicit to prevent an assertion when it's added
-      // to an instruction. This is a temporary workaround until the implicit
-      // register flag can be parsed.
-      if (Operands[I].isReg())
-        Operands[I].setImplicit();
-    }
-  }
-
-  // TODO: Determine the implicit behaviour when implicit register flags are
-  // parsed.
+  // TODO: Check for extraneous machine operands.
+  // TODO: Check that this instruction has the implicit register operands.
   MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
   for (const auto &Operand : Operands)
     MI->addOperand(MF, Operand);
   return false;
 }
 
 bool MIParser::parseMBB(MachineBasicBlock *&MBB) {
   lex();
bool MIParser::parseRegister(unsigned &Reg) {
   }
   // TODO: Parse other register kinds.
   default:
     llvm_unreachable("The current token should be a register");
   }
   return false;
 }
 
+bool MIParser::parseRegisterFlag(unsigned &Flags) {
+  switch (Token.kind()) {
+  case MIToken::kw_implicit:
+    Flags |= RegState::Implicit;
+    break;
+  case MIToken::kw_implicit_define:
+    Flags |= RegState::ImplicitDefine;
+    break;
+  // TODO: report an error when we specify the same flag more than once.
+  // TODO: parse the other register flags.
+  default:
+    llvm_unreachable("The current token should be a register flag");
+  }
+  lex();
+  return false;
+}
+
 bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
   unsigned Reg;
-  // TODO: Parse register flags.
+  unsigned Flags = IsDef ? RegState::Define : 0;
+  while (Token.isRegisterFlag()) {
+    if (parseRegisterFlag(Flags))
+      return true;
+  }
+  if (!Token.isRegister())
+    return error("expected a register after register flags");
   if (parseRegister(Reg))
     return true;
   lex();
   // TODO: Parse subregister.
-  Dest = MachineOperand::CreateReg(Reg, IsDef);
+  Dest = MachineOperand::CreateReg(Reg, Flags & RegState::Define,
+                                   Flags & RegState::Implicit);
   return false;
 }
 
 bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::IntegerLiteral));
   const APSInt &Int = Token.integerValue();
   if (Int.getMinSignedBits() > 64)
     // TODO: Replace this with an error when we can parse CIMM Machine Operands.
bool MIParser::parseGlobalAddressOperand(MachineOperand &Dest) {
   }
   // TODO: Parse offset and target flags.
   lex();
   return false;
 }
 
 bool MIParser::parseMachineOperand(MachineOperand &Dest) {
   switch (Token.kind()) {
+  case MIToken::kw_implicit:
+  case MIToken::kw_implicit_define:
   case MIToken::underscore:
   case MIToken::NamedRegister:
     return parseRegisterOperand(Dest);
   case MIToken::IntegerLiteral:
     return parseImmediateOperand(Dest);
   case MIToken::MachineBasicBlock:
     return parseMBBOperand(Dest);
   case MIToken::GlobalValue:

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

if (const auto *BB = MBB.getBasicBlock()) {
     if (BB->hasName())
       OS << '.' << BB->getName();
   }
 }
 
 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
   switch (Op.getType()) {
   case MachineOperand::MO_Register:
-    // TODO: Print register flags.
+    // TODO: Print the other register flags.
+    if (Op.isImplicit())
+      OS << (Op.isDef() ? "implicit-def " : "implicit ");
     printReg(Op.getReg(), OS, TRI);
     // TODO: Print sub register.
     break;
   case MachineOperand::MO_Immediate:
     OS << Op.getImm();
     break;
   case MachineOperand::MO_MachineBasicBlock:
     printMBBReference(*Op.getMBB());

llvm/trunk/test/CodeGen/MIR/X86/expected-register-after-flags.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when a register operand doesn't
+# follow register flags.
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body:
+ - id:           0
+   name:         entry
+   instructions:
+     # CHECK: [[@LINE+1]]:37: expected a register after register flags
+     - '%eax = MOV32r0 implicit-def 2'
+     - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir

+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'implicit' and 'implicit-def'
+# register flags correctly.
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body:
+  - id:          0
+    name:        entry
+    instructions:
+      # CHECK:      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
+      # CHECK-NEXT: - 'JG_1 %bb.2.exit, implicit %eflags'
+      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
+      - 'JG_1 %bb.2.exit, implicit %eflags'
+  - id:          1
+    name:        less
+    instructions:
+      # CHECK: - '%eax = MOV32r0 implicit-def %eflags'
+      - '%eax = MOV32r0 implicit-def %eflags'
+      - 'RETQ %eax'
+  - id:          2
+    name:        exit
+    instructions:
+      - '%eax = COPY %edi'
+      - 'RETQ %eax'
+...

llvm/trunk/test/CodeGen/MIR/X86/register-mask-operands.mir

 ---
 # CHECK: name: foo
 name:            foo
 body:
   - id:          0
     name:        entry
     instructions:
       # CHECK:      - 'PUSH64r %rax
-      # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, %rsp, %edi, %rsp, %eax'
+      # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
       - 'PUSH64r %rax'
-      - 'CALL64pcrel32 @compute, csr_64, %rsp, %edi, %rsp, %eax'
+      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
       - '%rdx = POP64r'
       - 'RETQ %eax'
 ...