Add support for nest attribute to AArch64 backend

[• scross99]

Summary

The nest attribute is currently supported on the x86 (32-bit) and x86-64 backends, but not on ARM (32-bit) or AArch64. This patch adds support for nest to the AArch64 backend.

Register x18 is used by GCC for this purpose (see https://github.com/gcc-mirror/gcc/blob/7c62dfbbcd3699efcbbadc9fb3aa14f23a123add/gcc/testsuite/gcc.dg/cwsc1.c ) and hence is used here. As discussed on the GCC mailing list (see http://www.mail-archive.com/[e-mail]/msg76966.html ) the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible.

A slight complexity to this issue is that x18 is reserved as the 'platform register' on iOS and Mac (see https://developer.apple.com/library/ios/documentation/Xcode/Conceptual/iPhoneOSABIReference/Articles/ARM64FunctionCallingConventions.html ) and no register has been selected by GCC yet, so nest remains unsupported for those platforms.

Relevant LLVM mailing list discussion: http://comments.gmane.org/gmane.comp.compilers.llvm.devel/86370

[• scross99]

Has anyone had a chance to look at this change (allowing for understandably busy schedules)?

[t.p.northover]

Hi, sorry for the delay. I think the change itself looks reasonable. Just one question about the test...

test/CodeGen/AArch64/nest-register.ll

8

Have you checked this on a non-asserts build? I'm never really sure what gets skipped in the name of efficiency.

[• scross99]

test/CodeGen/AArch64/nest-register.ll

8

Yes, this was tested on a Release build of LLVM with assertions off. Are you suggesting that enabling assertions might catch a problem with this line (I manually verified the output so this shouldn't happen) or that a Release build might not emit the assembly comment?

I did a bit of digging and found that neon-bitcast.ll (Git mirror link: https://github.com/llvm-mirror/llvm/blob/master/test/CodeGen/AArch64/neon-bitcast.ll ) has very similar code, such as:

define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
; CHECK: test_v8i8_to_v1i64:
; CHECK-NEXT: // BB#0:
; CHECK-NEXT: ret

  %val = bitcast <8 x i8> %in to <1 x i64>
  ret <1 x i64> %val
}

I'm very happy to do further testing with different configurations if needed.

[t.p.northover]

Yes, this was tested on a Release build of LLVM with assertions off.

Oh good, seems fine then.

Are you suggesting that enabling assertions might catch a problem with this line (I manually verified the output so this shouldn't happen) or that a Release build might not emit the assembly comment?

The latter (I've been caught out by a flurry of bot complaints
before). But if you've tested it then that's fine.

Cheers.

Tim.

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[• scross99]

Oh good, seems fine then.

I don't have commit rights; could you commit this for me?

[• scross99]

(Ping.)

[rengolin]

Committed as r241794.

[• scross99]

Thanks for committing this, however it looks like the test wasn't committed (only the change to the backend code).

[rengolin]

Ooops, sorry! r241797

[• scross99]

Ooops, sorry! r241797

No problem. Thanks again :-).

lib/Target/AArch64/AArch64CallingConvention.td

def CC_AArch64_AAPCS : CallingConv<[
 
   // An SRet is passed in X8, not X0 like a normal pointer parameter.
   CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
 
   // Put ByVal arguments directly on the stack. Minimum size and alignment of a
   // slot is 64-bit.
   CCIfByVal<CCPassByVal<8, 8>>,
 
+  // The 'nest' parameter, if any, is passed in X18.
+  // Darwin uses X18 as the platform register and hence 'nest' isn't currently
+  // supported there.
+  CCIfNest<CCAssignToReg<[X18]>>,
+
   CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
 
   // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
   // up to eight each of GPR and FPR.
   CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
   CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
                                           [X0, X1, X2, X3, X4, X5, X6, X7]>>,
   // i128 is split to two i64s, we can't fit half to register X7.

test/CodeGen/AArch64/nest-register.ll

+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
+
+; Tests that the 'nest' parameter attribute causes the relevant parameter to be
+; passed in the right register.
+
+define i8* @nest_receiver(i8* nest %arg) nounwind {
+; CHECK-LABEL: nest_receiver:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: mov x0, x18
+; CHECK-NEXT: ret
+
+  ret i8* %arg
+}
+
+define i8* @nest_caller(i8* %arg) nounwind {
+; CHECK-LABEL: nest_caller:
+; CHECK: mov x18, x0
+; CHECK-NEXT: bl nest_receiver
+; CHECK: ret
+
+  %result = call i8* @nest_receiver(i8* nest %arg)
+  ret i8* %result
+}