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Differential D10513

ARM: Enable MachineScheduler and disable PostRAScheduler for swift CPU.
ClosedPublic

Authored by MatzeB on Jun 17 2015, 11:58 AM.

Details

Reviewers
grosbach
atrick
Commits
rG9e85980658ad: ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
rG2d8315f8066b: ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
rL242588: ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
rL242500: ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
Summary

This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in swift
in favor of the SchedModel one.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

Diff Detail

Repository
rL LLVM

Event Timeline

MatzeB updated this revision to Diff 27858.Jun 17 2015, 11:58 AM
MatzeB retitled this revision from to ARM: Enable MachineScheduler and disable PostRAScheduler for swift CPU..
MatzeB updated this object.
MatzeB edited the test plan for this revision. (Show Details)
MatzeB added reviewers: grosbach, atrick.
MatzeB set the repository for this revision to rL LLVM.
MatzeB added a subscriber: Unknown Object (MLST).
Herald added subscribers: aemerson, rengolin. · View Herald TranscriptJun 17 2015, 11:58 AM
atrick accepted this revision.Jul 16 2015, 3:28 PM
atrick edited edge metadata.

Thank you Matthias. Sorry I dropped the review.

If you think isOutOfOrder is a useful helper, then you can just add it to the MCSchedModel interface. I don't think there's anything ARM specific about it.

This revision is now accepted and ready to land.Jul 16 2015, 3:28 PM
Closed by commit rL242500: ARM: Enable MachineScheduler and disable PostRAScheduler for swift. (authored by matze). · Explain WhyJul 16 2015, 6:44 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
MC/
3 lines
lib/
Target/
ARM/
1038 lines
3 lines
11 lines
test/
CodeGen/
ARM/
14 lines
16 lines
6 lines
16 lines
4 lines
6 lines

Diff 29970

llvm/trunk/include/llvm/MC/MCSchedule.h

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Linesstruct MCSchedModel {
/// Does this machine model include instruction-level scheduling. /// Does this machine model include instruction-level scheduling.
bool hasInstrSchedModel() const { return SchedClassTable; } bool hasInstrSchedModel() const { return SchedClassTable; }
/// Return true if this machine model data for all instructions with a /// Return true if this machine model data for all instructions with a
/// scheduling class (itinerary class or SchedRW list). /// scheduling class (itinerary class or SchedRW list).
bool isComplete() const { return CompleteModel; } bool isComplete() const { return CompleteModel; }
/// Return true if machine supports out of order execution.
bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
unsigned getNumProcResourceKinds() const { unsigned getNumProcResourceKinds() const {
return NumProcResourceKinds; return NumProcResourceKinds;
} }
const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const { const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
assert(hasInstrSchedModel() && "No scheduling machine model"); assert(hasInstrSchedModel() && "No scheduling machine model");
assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx"); assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
Show All 18 Lines

llvm/trunk/lib/Target/ARM/ARMScheduleSwift.td

Show All 31 Lines
// FIXME: Do we need to model the fact that uses of r15 in a micro-op force it // FIXME: Do we need to model the fact that uses of r15 in a micro-op force it
// to issue on pipe 1? // to issue on pipe 1?
// FIXME: Model the pipelined behavior of CMP / TST instructions. // FIXME: Model the pipelined behavior of CMP / TST instructions.
// FIXME: Better model the microcode stages of multiply instructions, especially // FIXME: Better model the microcode stages of multiply instructions, especially
// conditional variants. // conditional variants.
// FIXME: Add preload instruction when it is documented. // FIXME: Add preload instruction when it is documented.
// FIXME: Model non-pipelined nature of FP div / sqrt unit. // FIXME: Model non-pipelined nature of FP div / sqrt unit.
def SwiftItineraries : ProcessorItineraries<
[SW_DIS0, SW_DIS1, SW_DIS2, SW_ALU0, SW_ALU1, SW_LS, SW_IDIV, SW_FDIV], [], [
//
// Move instructions, unconditional
InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMOVsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMOVix2 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2]>,
InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>,
InstrStage<1, [SW_ALU0, SW_ALU1]>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[3]>,
InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>,
InstrStage<1, [SW_ALU0, SW_ALU1]>,
InstrStage<1, [SW_LS]>],
[5]>,
//
// MVN instructions
InstrItinData<IIC_iMVNi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMVNr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMVNsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iMVNsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
//
// No operand cycles
InstrItinData<IIC_iALUx , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>]>,
//
// Binary Instructions that produce a result
InstrItinData<IIC_iALUi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iALUr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1, 1]>,
InstrItinData<IIC_iALUsi, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1]>,
InstrItinData<IIC_iALUsir,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1]>,
InstrItinData<IIC_iALUsr, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1, 1]>,
//
// Bitwise Instructions that produce a result
InstrItinData<IIC_iBITi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iBITr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1, 1]>,
InstrItinData<IIC_iBITsi, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1]>,
InstrItinData<IIC_iBITsr, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1, 1]>,
//
// Unary Instructions that produce a result
// CLZ, RBIT, etc.
InstrItinData<IIC_iUNAr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
// BFC, BFI, UBFX, SBFX
InstrItinData<IIC_iUNAsi, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1]>,
//
// Zero and sign extension instructions
InstrItinData<IIC_iEXTr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iEXTAr, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1, 1]>,
InstrItinData<IIC_iEXTAsr,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1, 1, 1]>,
//
// Compare instructions
InstrItinData<IIC_iCMPi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iCMPr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iCMPsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<2, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iCMPsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<2, [SW_ALU0, SW_ALU1]>],
[1, 1, 1]>,
//
// Test instructions
InstrItinData<IIC_iTSTi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iTSTr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iTSTsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<2, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iTSTsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<2, [SW_ALU0, SW_ALU1]>],
[1, 1, 1]>,
//
// Move instructions, conditional
// FIXME: Correctly model the extra input dep on the destination.
InstrItinData<IIC_iCMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
InstrItinData<IIC_iCMOVr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iCMOVsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1, 1]>,
InstrItinData<IIC_iCMOVsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1]>,
InstrItinData<IIC_iCMOVix2, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2]>,
// Integer multiply pipeline
//
InstrItinData<IIC_iMUL16 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[3, 1, 1]>,
InstrItinData<IIC_iMAC16 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[3, 1, 1, 1]>,
InstrItinData<IIC_iMUL32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
InstrItinData<IIC_iMAC32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1, 1]>,
InstrItinData<IIC_iMUL64 , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0], 1>,
InstrStage<1, [SW_ALU0], 3>,
InstrStage<1, [SW_ALU0]>],
[5, 5, 1, 1]>,
InstrItinData<IIC_iMAC64 , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0], 1>,
InstrStage<1, [SW_ALU0], 1>,
InstrStage<1, [SW_ALU0, SW_ALU1], 3>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[5, 6, 1, 1]>,
//
// Integer divide
InstrItinData<IIC_iDIV , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0], 0>,
InstrStage<14, [SW_IDIV]>],
[14, 1, 1]>,
// Integer load pipeline
// FIXME: The timings are some rough approximations
//
// Immediate offset
InstrItinData<IIC_iLoad_i , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[3, 1]>,
InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[3, 1]>,
InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 1>,
InstrStage<1, [SW_LS]>],
[3, 4, 1]>,
//
// Register offset
InstrItinData<IIC_iLoad_r , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[3, 1, 1]>,
InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[3, 1, 1]>,
InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_LS], 1>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[3, 4, 1, 1]>,
//
// Scaled register offset
InstrItinData<IIC_iLoad_si , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS]>],
[5, 1, 1]>,
InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS]>],
[5, 1, 1]>,
//
// Immediate offset with update
InstrItinData<IIC_iLoad_iu , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[3, 1, 1]>,
InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[3, 1, 1]>,
//
// Register offset with update
InstrItinData<IIC_iLoad_ru , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0], 1>,
InstrStage<1, [SW_LS]>],
[3, 1, 1, 1]>,
InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0], 1>,
InstrStage<1, [SW_LS]>],
[3, 1, 1, 1]>,
InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 0>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_LS], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[3, 4, 1, 1]>,
//
// Scaled register offset with update
InstrItinData<IIC_iLoad_siu , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[5, 3, 1, 1]>,
InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[5, 3, 1, 1]>,
//
// Load multiple, def is the 5th operand.
// FIXME: This assumes 3 to 4 registers.
InstrItinData<IIC_iLoad_m , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1, 1, 3], [], -1>, // dynamic uops
//
// Load multiple + update, defs are the 1st and 5th operands.
InstrItinData<IIC_iLoad_mu , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 0>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1, 1, 3], [], -1>, // dynamic uops
//
// Load multiple plus branch
InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1, 1, 3], [], -1>, // dynamic uops
//
// Pop, def is the 3rd operand.
InstrItinData<IIC_iPop , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 3], [], -1>, // dynamic uops
//
// Pop + branch, def is the 3rd operand.
InstrItinData<IIC_iPop_Br, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 3], [], -1>, // dynamic uops
//
// iLoadi + iALUr for t2LDRpci_pic.
InstrItinData<IIC_iLoadiALU, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[4, 1]>,
// Integer store pipeline
///
// Immediate offset
InstrItinData<IIC_iStore_i , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1]>,
InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1]>,
InstrItinData<IIC_iStore_d_i, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_LS], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1]>,
//
// Register offset
InstrItinData<IIC_iStore_r , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
InstrItinData<IIC_iStore_d_r, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_LS], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
//
// Scaled register offset
InstrItinData<IIC_iStore_si , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
//
// Immediate offset with update
InstrItinData<IIC_iStore_iu , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1]>,
//
// Register offset with update
InstrItinData<IIC_iStore_ru , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1, 1]>,
InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1, 1]>,
InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[1, 1, 1, 1]>,
//
// Scaled register offset with update
InstrItinData<IIC_iStore_siu, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>],
[3, 1, 1, 1]>,
InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 2>,
InstrStage<1, [SW_LS], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>],
[3, 1, 1, 1]>,
//
// Store multiple
InstrItinData<IIC_iStore_m , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS], 1>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS], 1>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[], [], -1>, // dynamic uops
//
// Store multiple + update
InstrItinData<IIC_iStore_mu, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS], 1>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS], 1>,
InstrStage<1, [SW_ALU0, SW_ALU1], 1>,
InstrStage<1, [SW_LS]>],
[2], [], -1>, // dynamic uops
//
// Preload
InstrItinData<IIC_Preload, [InstrStage<1, [SW_DIS0], 0>], [1, 1]>,
// Branch
//
// no delay slots, so the latency of a branch is unimportant
InstrItinData<IIC_Br , [InstrStage<1, [SW_DIS0], 0>]>,
// FP Special Register to Integer Register File Move
InstrItinData<IIC_fpSTAT , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[1]>,
//
// Single-precision FP Unary
//
// Most floating-point moves get issued on ALU0.
InstrItinData<IIC_fpUNA32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1]>,
//
// Double-precision FP Unary
InstrItinData<IIC_fpUNA64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1]>,
//
// Single-precision FP Compare
InstrItinData<IIC_fpCMP32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[1, 1]>,
//
// Double-precision FP Compare
InstrItinData<IIC_fpCMP64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[1, 1]>,
//
// Single to Double FP Convert
InstrItinData<IIC_fpCVTSD , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Double to Single FP Convert
InstrItinData<IIC_fpCVTDS , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Single to Half FP Convert
InstrItinData<IIC_fpCVTSH , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU1], 4>,
InstrStage<1, [SW_ALU1]>],
[6, 1]>,
//
// Half to Single FP Convert
InstrItinData<IIC_fpCVTHS , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Single-Precision FP to Integer Convert
InstrItinData<IIC_fpCVTSI , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Double-Precision FP to Integer Convert
InstrItinData<IIC_fpCVTDI , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Integer to Single-Precision FP Convert
InstrItinData<IIC_fpCVTIS , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Integer to Double-Precision FP Convert
InstrItinData<IIC_fpCVTID , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1]>,
//
// Single-precision FP ALU
InstrItinData<IIC_fpALU32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Double-precision FP ALU
InstrItinData<IIC_fpALU64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Single-precision FP Multiply
InstrItinData<IIC_fpMUL32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Double-precision FP Multiply
InstrItinData<IIC_fpMUL64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[6, 1, 1]>,
//
// Single-precision FP MAC
InstrItinData<IIC_fpMAC32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Double-precision FP MAC
InstrItinData<IIC_fpMAC64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[12, 1, 1]>,
//
// Single-precision Fused FP MAC
InstrItinData<IIC_fpFMAC32, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Double-precision Fused FP MAC
InstrItinData<IIC_fpFMAC64, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[12, 1, 1]>,
//
// Single-precision FP DIV
InstrItinData<IIC_fpDIV32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 0>,
InstrStage<15, [SW_FDIV]>],
[17, 1, 1]>,
//
// Double-precision FP DIV
InstrItinData<IIC_fpDIV64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 0>,
InstrStage<30, [SW_FDIV]>],
[32, 1, 1]>,
//
// Single-precision FP SQRT
InstrItinData<IIC_fpSQRT32, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 0>,
InstrStage<15, [SW_FDIV]>],
[17, 1]>,
//
// Double-precision FP SQRT
InstrItinData<IIC_fpSQRT64, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 0>,
InstrStage<30, [SW_FDIV]>],
[32, 1, 1]>,
//
// Integer to Single-precision Move
InstrItinData<IIC_fpMOVIS, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 4>,
InstrStage<1, [SW_ALU0]>],
[6, 1]>,
//
// Integer to Double-precision Move
InstrItinData<IIC_fpMOVID, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[4, 1]>,
//
// Single-precision to Integer Move
InstrItinData<IIC_fpMOVSI, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[3, 1]>,
//
// Double-precision to Integer Move
InstrItinData<IIC_fpMOVDI, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_LS]>],
[3, 4, 1]>,
//
// Single-precision FP Load
InstrItinData<IIC_fpLoad32, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[4, 1]>,
//
// Double-precision FP Load
InstrItinData<IIC_fpLoad64, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[4, 1]>,
//
// FP Load Multiple
// FIXME: Assumes a single Q register.
InstrItinData<IIC_fpLoad_m, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1, 1, 4], [], -1>, // dynamic uops
//
// FP Load Multiple + update
// FIXME: Assumes a single Q register.
InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 4>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1, 1, 4], [], -1>, // dynamic uops
//
// Single-precision FP Store
InstrItinData<IIC_fpStore32,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1]>,
//
// Double-precision FP Store
InstrItinData<IIC_fpStore64,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1]>,
//
// FP Store Multiple
// FIXME: Assumes a single Q register.
InstrItinData<IIC_fpStore_m,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[1, 1, 1], [], -1>, // dynamic uops
//
// FP Store Multiple + update
// FIXME: Assumes a single Q register.
InstrItinData<IIC_fpStore_mu,[InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 4>,
InstrStage<1, [SW_ALU0, SW_ALU1]>],
[2, 1, 1, 1], [], -1>, // dynamic uops
// NEON
//
// Double-register Integer Unary
InstrItinData<IIC_VUNAiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1]>,
//
// Quad-register Integer Unary
InstrItinData<IIC_VUNAiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1]>,
//
// Double-register Integer Q-Unary
InstrItinData<IIC_VQUNAiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1]>,
//
// Quad-register Integer CountQ-Unary
InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1]>,
//
// Double-register Integer Binary
InstrItinData<IIC_VBINiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Quad-register Integer Binary
InstrItinData<IIC_VBINiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Double-register Integer Subtract
InstrItinData<IIC_VSUBiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Quad-register Integer Subtract
InstrItinData<IIC_VSUBiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Double-register Integer Shift
InstrItinData<IIC_VSHLiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Quad-register Integer Shift
InstrItinData<IIC_VSHLiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Double-register Integer Shift (4 cycle)
InstrItinData<IIC_VSHLi4D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Quad-register Integer Shift (4 cycle)
InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Double-register Integer Binary (4 cycle)
InstrItinData<IIC_VBINi4D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Quad-register Integer Binary (4 cycle)
InstrItinData<IIC_VBINi4Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Double-register Integer Subtract (4 cycle)
InstrItinData<IIC_VSUBi4D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Quad-register Integer Subtract (4 cycle)
InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Double-register Integer Count
InstrItinData<IIC_VCNTiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Quad-register Integer Count
InstrItinData<IIC_VCNTiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1, 1]>,
//
// Double-register Absolute Difference and Accumulate
InstrItinData<IIC_VABAD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1, 1]>,
//
// Quad-register Absolute Difference and Accumulate
InstrItinData<IIC_VABAQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1, 1]>,
//
// Double-register Integer Pair Add Long
InstrItinData<IIC_VPALiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Quad-register Integer Pair Add Long
InstrItinData<IIC_VPALiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Double-register Integer Multiply (.8, .16)
InstrItinData<IIC_VMULi16D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Quad-register Integer Multiply (.8, .16)
InstrItinData<IIC_VMULi16Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Double-register Integer Multiply (.32)
InstrItinData<IIC_VMULi32D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Quad-register Integer Multiply (.32)
InstrItinData<IIC_VMULi32Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Double-register Integer Multiply-Accumulate (.8, .16)
InstrItinData<IIC_VMACi16D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1, 1]>,
//
// Double-register Integer Multiply-Accumulate (.32)
InstrItinData<IIC_VMACi32D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1, 1]>,
//
// Quad-register Integer Multiply-Accumulate (.8, .16)
InstrItinData<IIC_VMACi16Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1, 1]>,
//
// Quad-register Integer Multiply-Accumulate (.32)
InstrItinData<IIC_VMACi32Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1, 1]>,
//
// Move
InstrItinData<IIC_VMOV, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1]>,
//
// Move Immediate
InstrItinData<IIC_VMOVImm, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2]>,
//
// Double-register Permute Move
InstrItinData<IIC_VMOVD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1]>,
//
// Quad-register Permute Move
InstrItinData<IIC_VMOVQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1]>,
//
// Integer to Single-precision Move
InstrItinData<IIC_VMOVIS , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 4>,
InstrStage<1, [SW_ALU0]>],
[6, 1]>,
//
// Integer to Double-precision Move
InstrItinData<IIC_VMOVID , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[4, 1, 1]>,
//
// Single-precision to Integer Move
InstrItinData<IIC_VMOVSI , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_LS]>],
[3, 1]>,
//
// Double-precision to Integer Move
InstrItinData<IIC_VMOVDI , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 3>,
InstrStage<1, [SW_LS]>],
[3, 4, 1]>,
//
// Integer to Lane Move
// FIXME: I think this is correct, but it is not clear from the tuning guide.
InstrItinData<IIC_VMOVISL , [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_LS], 4>,
InstrStage<1, [SW_ALU0]>],
[6, 1]>,
//
// Vector narrow move
InstrItinData<IIC_VMOVN, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1]>,
//
// Double-register FP Unary
// FIXME: VRECPE / VRSQRTE has a longer latency than VABS, which is used here,
// and they issue on a different pipeline.
InstrItinData<IIC_VUNAD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1]>,
//
// Quad-register FP Unary
// FIXME: VRECPE / VRSQRTE has a longer latency than VABS, which is used here,
// and they issue on a different pipeline.
InstrItinData<IIC_VUNAQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[2, 1]>,
//
// Double-register FP Binary
// FIXME: We're using this itin for many instructions.
InstrItinData<IIC_VBIND, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// VPADD, etc.
InstrItinData<IIC_VPBIND, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Double-register FP VMUL
InstrItinData<IIC_VFMULD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Quad-register FP Binary
InstrItinData<IIC_VBINQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU0]>],
[4, 1, 1]>,
//
// Quad-register FP VMUL
InstrItinData<IIC_VFMULQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 1]>,
//
// Double-register FP Multiple-Accumulate
InstrItinData<IIC_VMACD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Quad-register FP Multiple-Accumulate
InstrItinData<IIC_VMACQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Double-register Fused FP Multiple-Accumulate
InstrItinData<IIC_VFMACD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Quad-register FusedF P Multiple-Accumulate
InstrItinData<IIC_VFMACQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Double-register Reciprical Step
InstrItinData<IIC_VRECSD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Quad-register Reciprical Step
InstrItinData<IIC_VRECSQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 1]>,
//
// Double-register Permute
// FIXME: The latencies are unclear from the documentation.
InstrItinData<IIC_VPERMD, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[3, 4, 3, 4]>,
//
// Quad-register Permute
// FIXME: The latencies are unclear from the documentation.
InstrItinData<IIC_VPERMQ, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[3, 4, 3, 4]>,
//
// Quad-register Permute (3 cycle issue on A9)
InstrItinData<IIC_VPERMQ3, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[3, 4, 3, 4]>,
//
// Double-register VEXT
InstrItinData<IIC_VEXTD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1, 1]>,
//
// Quad-register VEXT
InstrItinData<IIC_VEXTQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1, 1]>,
//
// VTB
InstrItinData<IIC_VTB1, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1, 1]>,
InstrItinData<IIC_VTB2, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 3, 3]>,
InstrItinData<IIC_VTB3, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[6, 1, 3, 5, 5]>,
InstrItinData<IIC_VTB4, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 3, 5, 7, 7]>,
//
// VTBX
InstrItinData<IIC_VTBX1, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>,
InstrStage<1, [SW_ALU1]>],
[2, 1, 1]>,
InstrItinData<IIC_VTBX2, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[4, 1, 3, 3]>,
InstrItinData<IIC_VTBX3, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[6, 1, 3, 5, 5]>,
InstrItinData<IIC_VTBX4, [InstrStage<1, [SW_DIS0], 0>,
InstrStage<1, [SW_DIS1], 0>,
InstrStage<1, [SW_DIS2], 0>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1], 2>,
InstrStage<1, [SW_ALU1]>],
[8, 1, 3, 5, 7, 7]>
]>;
// ===---------------------------------------------------------------------===//
// This following definitions describe the simple machine model which
// will replace itineraries.
// Swift machine model for scheduling and other instruction cost heuristics. // Swift machine model for scheduling and other instruction cost heuristics.
def SwiftModel : SchedMachineModel { def SwiftModel : SchedMachineModel {
let IssueWidth = 3; // 3 micro-ops are dispatched per cycle. let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
let MicroOpBufferSize = 45; // Based on NEON renamed registers. let MicroOpBufferSize = 45; // Based on NEON renamed registers.
let LoadLatency = 3; let LoadLatency = 3;
let MispredictPenalty = 14; // A branch direction mispredict. let MispredictPenalty = 14; // A branch direction mispredict.
let Itineraries = SwiftItineraries;
} }
// Swift predicates. // Swift predicates.
def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>; def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>;
// Swift resource mapping. // Swift resource mapping.
let SchedModel = SwiftModel in { let SchedModel = SwiftModel in {
// Processor resources. // Processor resources.
▲ Show 20 Lines • Show All 985 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

Show First 20 Lines • Show All 427 Lines • ▼ Show 20 Linespublic:
bool isLittle() const { return IsLittle; } bool isLittle() const { return IsLittle; }
unsigned getMispredictionPenalty() const; unsigned getMispredictionPenalty() const;
/// This function returns true if the target has sincos() routine in its /// This function returns true if the target has sincos() routine in its
/// compiler runtime or math libraries. /// compiler runtime or math libraries.
bool hasSinCos() const; bool hasSinCos() const;
/// Returns true if machine scheduler should be enabled.
bool enableMachineScheduler() const override;
/// True for some subtargets at > -O0. /// True for some subtargets at > -O0.
bool enablePostRAScheduler() const override; bool enablePostRAScheduler() const override;
// enableAtomicExpand- True if we need to expand our atomics. // enableAtomicExpand- True if we need to expand our atomics.
bool enableAtomicExpand() const override; bool enableAtomicExpand() const override;
/// getInstrItins - Return the instruction itineraries based on subtarget /// getInstrItins - Return the instruction itineraries based on subtarget
/// selection. /// selection.
Show All 19 Lines

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
unsigned ARMSubtarget::getMispredictionPenalty() const { unsigned ARMSubtarget::getMispredictionPenalty() const {
return SchedModel.MispredictPenalty; return SchedModel.MispredictPenalty;
} }
bool ARMSubtarget::hasSinCos() const { bool ARMSubtarget::hasSinCos() const {
return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0); return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
} }
bool ARMSubtarget::enableMachineScheduler() const {
// Enable the MachineScheduler before register allocation for out-of-order
// architectures where we do not use the PostRA scheduler anymore (for now
// restricted to swift).
return getSchedModel().isOutOfOrder() && isSwift();
}
// This overrides the PostRAScheduler bit in the SchedModel for any CPU. // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool ARMSubtarget::enablePostRAScheduler() const { bool ARMSubtarget::enablePostRAScheduler() const {
// No need for PostRA scheduling on out of order CPUs (for now restricted to
// swift).
if (getSchedModel().isOutOfOrder() && isSwift())
return false;
return (!isThumb() || hasThumb2()); return (!isThumb() || hasThumb2());
} }
bool ARMSubtarget::enableAtomicExpand() const { bool ARMSubtarget::enableAtomicExpand() const {
return hasAnyDataBarrier() && !isThumb1Only(); return hasAnyDataBarrier() && !isThumb1Only();
} }
bool ARMSubtarget::useMovt(const MachineFunction &MF) const { bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
Show All 14 Lines

llvm/trunk/test/CodeGen/ARM/adv-copy-opt.ll

; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s ; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s
; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s ; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s
; RUN: llc -O1 -mtriple=thumbv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s ; RUN: llc -O1 -mtriple=thumbv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s
; RUN: llc -O1 -mtriple=thumbv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s ; RUN: llc -O1 -mtriple=thumbv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s
; CHECK-LABEL: simpleVectorDiv ; CHECK-LABEL: simpleVectorDiv
; ABI: %A => r0, r1. ; ABI: %A => r0, r1.
; %B => r2, r3 ; %B => r2, r3
; ret => r0, r1 ; ret => r0, r1
; We want to compute: ; We want to compute:
; r0 = r0 / r2 ; r0 = r0 / r2
; r1 = r1 / r3 ; r1 = r1 / r3
; ;
; NOOPT: vmov [[B:d[0-9]+]], r2, r3 ; NOOPT: vmov [[A:d[0-9]+]], r0, r1
; NOOPT-NEXT: vmov [[A:d[0-9]+]], r0, r1 ; NOOPT-NEXT: vmov [[B:d[0-9]+]], r2, r3
; Move the low part of B into a register. ; Move the low part of B into a register.
; Unfortunately, we cannot express that the 's' register is the low ; Unfortunately, we cannot express that the 's' register is the low
; part of B, i.e., sIdx == BIdx x 2. E.g., B = d1, B_low = s2. ; part of B, i.e., sIdx == BIdx x 2. E.g., B = d1, B_low = s2.
; NOOPT-NEXT: vmov [[B_LOW:r[0-9]+]], s{{[0-9]+}} ; NOOPT-NEXT: vmov [[B_LOW:r[0-9]+]], s{{[0-9]+}}
; NOOPT-NEXT: vmov [[A_LOW:r[0-9]+]], s{{[0-9]+}}
; NOOPT-NEXT: udiv [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]]
; NOOPT-NEXT: vmov [[B_HIGH:r[0-9]+]], s{{[0-9]+}} ; NOOPT-NEXT: vmov [[B_HIGH:r[0-9]+]], s{{[0-9]+}}
; NOOPT-NEXT: vmov [[A_LOW:r[0-9]+]], s{{[0-9]+}}
; NOOPT-NEXT: vmov [[A_HIGH:r[0-9]+]], s{{[0-9]+}} ; NOOPT-NEXT: vmov [[A_HIGH:r[0-9]+]], s{{[0-9]+}}
; NOOPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]] ; NOOPT-NEXT: udiv [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]]
; NOOPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]] ; NOOPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]]
; NOOPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]]
; NOOPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]] ; NOOPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]]
; NOOPT-NEXT: vmov r0, r1, [[RES]] ; NOOPT-NEXT: vmov r0, r1, [[RES]]
; NOOPT-NEXT: bx lr ; NOOPT-NEXT: bx lr
; ;
; OPT-NOT: vmov ; OPT-NOT: vmov
; OPT: udiv r0, r0, r2 ; OPT: udiv r1, r1, r3
; OPT-NEXT: udiv r1, r1, r3 ; OPT-NEXT: udiv r0, r0, r2
; OPT-NEXT: bx lr ; OPT-NEXT: bx lr
define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind { define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind {
entry: entry:
%div = udiv <2 x i32> %A, %B %div = udiv <2 x i32> %A, %B
ret <2 x i32> %div ret <2 x i32> %div
} }

llvm/trunk/test/CodeGen/ARM/avoid-cpsr-rmw.ll

; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT
; Avoid some 's' 16-bit instruction which partially update CPSR (and add false ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
; dependency) when it isn't dependent on last CPSR defining instruction. ; dependency) when it isn't dependent on last CPSR defining instruction.
; rdar://8928208 ; rdar://8928208
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry: entry:
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 ; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2
; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 ; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0
; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r3
; CHECK-NEXT: muls r0, [[REG]], [[REG2]] ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
%0 = mul nsw i32 %a, %b %0 = mul nsw i32 %a, %b
%1 = mul nsw i32 %c, %d %1 = mul nsw i32 %c, %d
%2 = mul nsw i32 %0, %1 %2 = mul nsw i32 %0, %1
ret i32 %2 ret i32 %2
} }
; Avoid partial CPSR dependency via loop backedge. ; Avoid partial CPSR dependency via loop backedge.
; rdar://10357570 ; rdar://10357570
define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
entry: entry:
; CHECK-LABEL: t2: ; CHECK-LABEL: t2:
%tobool7 = icmp eq i32* %ptr2, null br label %while.body
br i1 %tobool7, label %while.end, label %while.body
while.body: while.body:
; CHECK: while.body ; CHECK: while.body
; CHECK: mul r{{[0-9]+}} ; CHECK: mul r{{[0-9]+}}
; CHECK-NOT: muls ; CHECK-NOT: muls
%ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
%ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
%0 = load i32, i32* %ptr1.addr.09, align 4 %0 = load i32, i32* %ptr1.addr.09, align 4
Show All 16 Lineswhile.end:
ret void ret void
} }
; Allow partial CPSR dependency when code size is the priority. ; Allow partial CPSR dependency when code size is the priority.
; rdar://12878928 ; rdar://12878928
define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
entry: entry:
; CHECK-LABEL: t3: ; CHECK-LABEL: t3:
%tobool7 = icmp eq i32* %ptr2, null br label %while.body
br i1 %tobool7, label %while.end, label %while.body
while.body: while.body:
; CHECK: while.body ; CHECK: while.body
; CHECK: mul r{{[0-9]+}} ; CHECK: mul r{{[0-9]+}}
; CHECK: muls ; CHECK: muls
%ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ] %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
%ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ] %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
%0 = load i32, i32* %ptr1.addr.09, align 4 %0 = load i32, i32* %ptr1.addr.09, align 4
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/ARM/cmpxchg-idioms.ll

Show All 9 Lines
; CHECK: cmp [[LOADED]], r1 ; CHECK: cmp [[LOADED]], r1
; CHECK: bne [[FAILED:LBB[0-9]+_[0-9]+]] ; CHECK: bne [[FAILED:LBB[0-9]+_[0-9]+]]
; CHECK: strex [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0] ; CHECK: strex [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0]
; CHECK: cmp [[STATUS]], #0 ; CHECK: cmp [[STATUS]], #0
; CHECK: bne [[LOOP]] ; CHECK: bne [[LOOP]]
; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: movs r0, #1
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK: movs r0, #1
; CHECK: bx lr ; CHECK: bx lr
; CHECK: [[FAILED]]: ; CHECK: [[FAILED]]:
; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: movs r0, #0
; CHECK: dmb ish ; CHECK: dmb ish
; CHECK: movs r0, #0
; CHECK: bx lr ; CHECK: bx lr
%pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
%success = extractvalue { i32, i1 } %pair, 1 %success = extractvalue { i32, i1 } %pair, 1
%conv = zext i1 %success to i32 %conv = zext i1 %success to i32
ret i32 %conv ret i32 %conv
} }
define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) { define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
; CHECK-LABEL: test_return_bool: ; CHECK-LABEL: test_return_bool:
; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1
; CHECK: dmb ishst ; CHECK: dmb ishst
; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1
; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexb [[LOADED:r[0-9]+]], [r0] ; CHECK: ldrexb [[LOADED:r[0-9]+]], [r0]
; CHECK: cmp [[LOADED]], [[OLDBYTE]] ; CHECK: cmp [[LOADED]], [[OLDBYTE]]
; CHECK: bne [[FAIL:LBB[0-9]+_[0-9]+]] ; CHECK: bne [[FAIL:LBB[0-9]+_[0-9]+]]
; CHECK: strexb [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0] ; CHECK: strexb [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0]
; CHECK: cmp [[STATUS]], #0 ; CHECK: cmp [[STATUS]], #0
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/ARM/test-sharedidx.ll

Show All 14 Lines
define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp { define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
entry: entry:
; CHECK-LABEL: sharedidx: ; CHECK-LABEL: sharedidx:
%cmp8 = icmp eq i32 %len, 0 %cmp8 = icmp eq i32 %len, 0
br i1 %cmp8, label %for.end, label %for.body br i1 %cmp8, label %for.end, label %for.body
for.body: ; preds = %entry, %for.body.3 for.body: ; preds = %entry, %for.body.3
; CHECK: %for.body ; CHECK: %for.body
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
%i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ] %i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]
%arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09 %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09
%0 = load i8, i8* %arrayidx, align 1 %0 = load i8, i8* %arrayidx, align 1
%conv6 = zext i8 %0 to i32 %conv6 = zext i8 %0 to i32
%arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09 %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09
%1 = load i8, i8* %arrayidx1, align 1 %1 = load i8, i8* %arrayidx1, align 1
%conv27 = zext i8 %1 to i32 %conv27 = zext i8 %1 to i32
%add = add nsw i32 %conv27, %conv6 %add = add nsw i32 %conv27, %conv6
%conv3 = trunc i32 %add to i8 %conv3 = trunc i32 %add to i8
%arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09 %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09
store i8 %conv3, i8* %arrayidx4, align 1 store i8 %conv3, i8* %arrayidx4, align 1
%add5 = add i32 %i.09, %s %add5 = add i32 %i.09, %s
%cmp = icmp ult i32 %add5, %len %cmp = icmp ult i32 %add5, %len
br i1 %cmp, label %for.body.1, label %for.end br i1 %cmp, label %for.body.1, label %for.end
for.end: ; preds = %for.body, %for.body.1, %for.body.2, %for.body.3, %entry for.end: ; preds = %for.body, %for.body.1, %for.body.2, %for.body.3, %entry
ret void ret void
for.body.1: ; preds = %for.body for.body.1: ; preds = %for.body
; CHECK: %for.body.1 ; CHECK: %for.body.1
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
%arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5 %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5
%2 = load i8, i8* %arrayidx.1, align 1 %2 = load i8, i8* %arrayidx.1, align 1
%conv6.1 = zext i8 %2 to i32 %conv6.1 = zext i8 %2 to i32
%arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5 %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5
%3 = load i8, i8* %arrayidx1.1, align 1 %3 = load i8, i8* %arrayidx1.1, align 1
%conv27.1 = zext i8 %3 to i32 %conv27.1 = zext i8 %3 to i32
%add.1 = add nsw i32 %conv27.1, %conv6.1 %add.1 = add nsw i32 %conv27.1, %conv6.1
%conv3.1 = trunc i32 %add.1 to i8 %conv3.1 = trunc i32 %add.1 to i8
%arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5 %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5
store i8 %conv3.1, i8* %arrayidx4.1, align 1 store i8 %conv3.1, i8* %arrayidx4.1, align 1
%add5.1 = add i32 %add5, %s %add5.1 = add i32 %add5, %s
%cmp.1 = icmp ult i32 %add5.1, %len %cmp.1 = icmp ult i32 %add5.1, %len
br i1 %cmp.1, label %for.body.2, label %for.end br i1 %cmp.1, label %for.body.2, label %for.end
for.body.2: ; preds = %for.body.1 for.body.2: ; preds = %for.body.1
; CHECK: %for.body.2 ; CHECK: %for.body.2
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
%arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1 %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1
%4 = load i8, i8* %arrayidx.2, align 1 %4 = load i8, i8* %arrayidx.2, align 1
%conv6.2 = zext i8 %4 to i32 %conv6.2 = zext i8 %4 to i32
%arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1 %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1
%5 = load i8, i8* %arrayidx1.2, align 1 %5 = load i8, i8* %arrayidx1.2, align 1
%conv27.2 = zext i8 %5 to i32 %conv27.2 = zext i8 %5 to i32
%add.2 = add nsw i32 %conv27.2, %conv6.2 %add.2 = add nsw i32 %conv27.2, %conv6.2
%conv3.2 = trunc i32 %add.2 to i8 %conv3.2 = trunc i32 %add.2 to i8
%arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1 %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1
store i8 %conv3.2, i8* %arrayidx4.2, align 1 store i8 %conv3.2, i8* %arrayidx4.2, align 1
%add5.2 = add i32 %add5.1, %s %add5.2 = add i32 %add5.1, %s
%cmp.2 = icmp ult i32 %add5.2, %len %cmp.2 = icmp ult i32 %add5.2, %len
br i1 %cmp.2, label %for.body.3, label %for.end br i1 %cmp.2, label %for.body.3, label %for.end
for.body.3: ; preds = %for.body.2 for.body.3: ; preds = %for.body.2
; CHECK: %for.body.3 ; CHECK: %for.body.3
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
; CHECK: ldrb {{r[0-9]|lr}}, [{{r[0-9]|lr}}, {{r[0-9]|lr}}]! ; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
%arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2 %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2
%6 = load i8, i8* %arrayidx.3, align 1 %6 = load i8, i8* %arrayidx.3, align 1
%conv6.3 = zext i8 %6 to i32 %conv6.3 = zext i8 %6 to i32
%arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2 %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2
%7 = load i8, i8* %arrayidx1.3, align 1 %7 = load i8, i8* %arrayidx1.3, align 1
%conv27.3 = zext i8 %7 to i32 %conv27.3 = zext i8 %7 to i32
%add.3 = add nsw i32 %conv27.3, %conv6.3 %add.3 = add nsw i32 %conv27.3, %conv6.3
%conv3.3 = trunc i32 %add.3 to i8 %conv3.3 = trunc i32 %add.3 to i8
%arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2 %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2
store i8 %conv3.3, i8* %arrayidx4.3, align 1 store i8 %conv3.3, i8* %arrayidx4.3, align 1
%add5.3 = add i32 %add5.2, %s %add5.3 = add i32 %add5.2, %s
%cmp.3 = icmp ult i32 %add5.3, %len %cmp.3 = icmp ult i32 %add5.3, %len
br i1 %cmp.3, label %for.body, label %for.end br i1 %cmp.3, label %for.body, label %for.end
} }

llvm/trunk/test/CodeGen/ARM/vector-load.ll

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Lines;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
%A = load <4 x i8>*, <4 x i8>** %ptr %A = load <4 x i8>*, <4 x i8>** %ptr
%lA = load <4 x i8>, <4 x i8>* %A, align 4 %lA = load <4 x i8>, <4 x i8>* %A, align 4
%zlA = zext <4 x i8> %lA to <4 x i32> %zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA ret <4 x i32> %zlA
} }
define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) { define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
;CHECK-LABEL: zextload_v8i8tov8i32_fake_update: ;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
;CHECK: ldr.w r[[PTRREG:[0-9]+]], [r0] ;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32] ;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16 ;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16
;CHECK: str.w r[[INCREG]], [r0]
;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} ;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} ;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
;CHECK: str r[[INCREG]], [r0]
%A = load <4 x i8>*, <4 x i8>** %ptr %A = load <4 x i8>*, <4 x i8>** %ptr
%lA = load <4 x i8>, <4 x i8>* %A, align 4 %lA = load <4 x i8>, <4 x i8>* %A, align 4
%inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4 %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
store <4 x i8>* %inc, <4 x i8>** %ptr store <4 x i8>* %inc, <4 x i8>** %ptr
%zlA = zext <4 x i8> %lA to <4 x i32> %zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA ret <4 x i32> %zlA
} }

llvm/trunk/test/CodeGen/ARM/vector-store.ll

Show First 20 Lines • Show All 222 Lines • ▼ Show 20 Lines;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
ret void ret void
} }
define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) { define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
;CHECK-LABEL: truncstore_v4i32tov4i8: ;CHECK-LABEL: truncstore_v4i32tov4i8:
;CHECK: ldr.w r9, [sp] ;CHECK: ldr.w r9, [sp]
;CHECK: vmov {{d[0-9]+}}, r3, r9 ;CHECK: vmov {{d[0-9]+}}, r3, r9
;CHECK: vmov {{d[0-9]+}}, r1, r2 ;CHECK: vmov {{d[0-9]+}}, r1, r2
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} ;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} ;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32] ;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32]
%A = load <4 x i8>*, <4 x i8>** %ptr %A = load <4 x i8>*, <4 x i8>** %ptr
%trunc = trunc <4 x i32> %val to <4 x i8> %trunc = trunc <4 x i32> %val to <4 x i8>
store <4 x i8> %trunc, <4 x i8>* %A, align 4 store <4 x i8> %trunc, <4 x i8>* %A, align 4
ret void ret void
} }
define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) { define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) {
;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update: ;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update:
;CHECK: ldr.w r9, [sp] ;CHECK: ldr.w r9, [sp]
;CHECK: vmov {{d[0-9]+}}, r3, r9 ;CHECK: vmov {{d[0-9]+}}, r3, r9
;CHECK: vmov {{d[0-9]+}}, r1, r2 ;CHECK: vmov {{d[0-9]+}}, r1, r2
;CHECK: movs [[IMM16:r[0-9]+]], #16 ;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} ;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} ;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] ;CHECK: movs [[IMM16:r[0-9]+]], #16
;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]] ;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]]
;CHECK: str r[[PTRREG]], [r0] ;CHECK: str r[[PTRREG]], [r0]
%A = load <4 x i8>*, <4 x i8>** %ptr %A = load <4 x i8>*, <4 x i8>** %ptr
%trunc = trunc <4 x i32> %val to <4 x i8> %trunc = trunc <4 x i32> %val to <4 x i8>
store <4 x i8> %trunc, <4 x i8>* %A, align 4 store <4 x i8> %trunc, <4 x i8>* %A, align 4
%inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4 %inc = getelementptr <4 x i8>, <4 x i8>* %A, i38 4
store <4 x i8>* %inc, <4 x i8>** %ptr store <4 x i8>* %inc, <4 x i8>** %ptr
ret void ret void
} }