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ARM: Enable MachineScheduler and disable PostRAScheduler for swift CPU.
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Authored by MatzeB on Jun 17 2015, 11:58 AM.

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Summary

This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in swift
in favor of the SchedModel one.

This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.

While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.

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rL LLVM

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MatzeB updated this revision to Diff 27858.Jun 17 2015, 11:58 AM
MatzeB retitled this revision from to ARM: Enable MachineScheduler and disable PostRAScheduler for swift CPU..
MatzeB updated this object.
MatzeB edited the test plan for this revision. (Show Details)
MatzeB added reviewers: grosbach, atrick.
MatzeB set the repository for this revision to rL LLVM.
MatzeB added a subscriber: Unknown Object (MLST).
atrick accepted this revision.Jul 16 2015, 3:28 PM
atrick edited edge metadata.

Thank you Matthias. Sorry I dropped the review.

If you think isOutOfOrder is a useful helper, then you can just add it to the MCSchedModel interface. I don't think there's anything ARM specific about it.

This revision is now accepted and ready to land.Jul 16 2015, 3:28 PM
This revision was automatically updated to reflect the committed changes.