This is an archive of the discontinued LLVM Phabricator instance.

Differential D10311

Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.
ClosedPublic

Authored by dsanders on Jun 8 2015, 5:40 AM.

Details

Reviewers
• rafael
Commits
rGa73f1fdb1967: Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and…
rL239467: Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and…
Summary

This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Depends on D10307

Diff Detail

Repository
rL LLVM

Event Timeline

dsanders updated this revision to Diff 27301.Jun 8 2015, 5:40 AM
dsanders retitled this revision from to Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC..
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added a parent revision: D10307: Replace string GNU Triples with llvm::Triple in create*MCRelocationInfo(). NFC..
dsanders added subscribers: rengolin, Unknown Object (MLST).
Herald added subscribers: jholewinski, jfb, ted. · View Herald TranscriptJun 8 2015, 5:40 AM
• rafael accepted this revision.Jun 9 2015, 1:32 PM
• rafael added a reviewer: • rafael.
• rafael added a subscriber: • rafael.

LGTM

This revision is now accepted and ready to land.Jun 9 2015, 1:32 PM
dsanders closed this revision.Jun 10 2015, 5:15 AM
Closed by commit rL239467: Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and… (authored by dsanders). · Explain WhyJun 10 2015, 5:15 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
include/
llvm/
MC/
11 lines
Support/
10 lines
lib/
MC/
17 lines
Target/
AArch64/
3 lines
8 lines
3 lines
MCTargetDesc/
2 lines
ARM/
2 lines
4 lines
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MCTargetDesc/
2 lines
10 lines
17 lines
BPF/
4 lines
2 lines
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MCTargetDesc/
4 lines
Hexagon/
2 lines
4 lines
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MCTargetDesc/
2 lines
MSP430/
MCTargetDesc/
4 lines
2 lines
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Mips/
MCTargetDesc/
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5 lines
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NVPTX/
MCTargetDesc/
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PowerPC/
MCTargetDesc/
4 lines
4 lines
2 lines
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R600/
7 lines
13 lines
4 lines
MCTargetDesc/
4 lines
Sparc/
AsmParser/
4 lines
MCTargetDesc/
7 lines
2 lines
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2 lines
SystemZ/
MCTargetDesc/
5 lines
2 lines
9 lines
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X86/
MCTargetDesc/
14 lines
11 lines
5 lines
2 lines
4 lines
XCore/
MCTargetDesc/
4 lines
4 lines
2 lines
2 lines
utils/
TableGen/
9 lines

Diff 27434

llvm/trunk/include/llvm/MC/MCSubtargetInfo.h

Show All 21 Lines
class StringRef; class StringRef;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// ///
/// MCSubtargetInfo - Generic base class for all target subtargets. /// MCSubtargetInfo - Generic base class for all target subtargets.
/// ///
class MCSubtargetInfo { class MCSubtargetInfo {
std::string TargetTriple; // Target triple Triple TargetTriple; // Target triple
std::string CPU; // CPU being targeted. std::string CPU; // CPU being targeted.
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
// Scheduler machine model // Scheduler machine model
const SubtargetInfoKV *ProcSchedModels; const SubtargetInfoKV *ProcSchedModels;
const MCWriteProcResEntry *WriteProcResTable; const MCWriteProcResEntry *WriteProcResTable;
const MCWriteLatencyEntry *WriteLatencyTable; const MCWriteLatencyEntry *WriteLatencyTable;
const MCReadAdvanceEntry *ReadAdvanceTable; const MCReadAdvanceEntry *ReadAdvanceTable;
MCSchedModel CPUSchedModel; MCSchedModel CPUSchedModel;
const InstrStage *Stages; // Instruction itinerary stages const InstrStage *Stages; // Instruction itinerary stages
const unsigned *OperandCycles; // Itinerary operand cycles const unsigned *OperandCycles; // Itinerary operand cycles
const unsigned *ForwardingPaths; // Forwarding paths const unsigned *ForwardingPaths; // Forwarding paths
FeatureBitset FeatureBits; // Feature bits for current CPU + FS FeatureBitset FeatureBits; // Feature bits for current CPU + FS
public: public:
void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetFeatureKV> PD, ArrayRef<SubtargetFeatureKV> PD,
const SubtargetInfoKV *ProcSched, const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR, const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const MCReadAdvanceEntry *RA, const InstrStage *IS,
const InstrStage *IS,
const unsigned *OC, const unsigned *FP); const unsigned *OC, const unsigned *FP);
/// getTargetTriple - Return the target triple string. /// getTargetTriple - Return the target triple string.
StringRef getTargetTriple() const { const Triple &getTargetTriple() const { return TargetTriple; }
return TargetTriple;
}
/// getCPU - Return the CPU string. /// getCPU - Return the CPU string.
StringRef getCPU() const { StringRef getCPU() const {
return CPU; return CPU;
} }
/// getFeatureBits - Return the feature bits. /// getFeatureBits - Return the feature bits.
/// ///
▲ Show 20 Lines • Show All 99 Lines • Show Last 20 Lines

llvm/trunk/include/llvm/Support/TargetRegistry.h

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Linespublic:
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
const Triple &TT); const Triple &TT);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model RM, typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info); typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo *Info);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(const Triple &TT,
StringRef CPU, StringRef CPU,
StringRef Features); StringRef Features);
typedef TargetMachine *(*TargetMachineCtorTy)( typedef TargetMachine *(*TargetMachineCtorTy)(
const Target &T, StringRef TT, StringRef CPU, StringRef Features, const Target &T, StringRef TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
// If it weren't for layering issues (this header is in llvm/Support, but // If it weren't for layering issues (this header is in llvm/Support, but
// depends on MC?) this should take the Streamer by value rather than rvalue // depends on MC?) this should take the Streamer by value rather than rvalue
▲ Show 20 Lines • Show All 219 Lines • ▼ Show 20 Linespublic:
MCRegisterInfo *createMCRegInfo(StringRef Triple) const { MCRegisterInfo *createMCRegInfo(StringRef Triple) const {
if (!MCRegInfoCtorFn) if (!MCRegInfoCtorFn)
return nullptr; return nullptr;
return MCRegInfoCtorFn(Triple); return MCRegInfoCtorFn(Triple);
} }
/// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
/// ///
/// \param Triple This argument is used to determine the target machine /// \param TheTriple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the /// either the target triple from the module, or the target triple of the
/// host if that does not exist. /// host if that does not exist.
/// \param CPU This specifies the name of the target CPU. /// \param CPU This specifies the name of the target CPU.
/// \param Features This specifies the string representation of the /// \param Features This specifies the string representation of the
/// additional target features. /// additional target features.
MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
StringRef Features) const { StringRef Features) const {
if (!MCSubtargetInfoCtorFn) if (!MCSubtargetInfoCtorFn)
return nullptr; return nullptr;
return MCSubtargetInfoCtorFn(Triple, CPU, Features); return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
} }
/// createTargetMachine - Create a target specific machine implementation /// createTargetMachine - Create a target specific machine implementation
/// for the specified \p Triple. /// for the specified \p Triple.
/// ///
/// \param Triple This argument is used to determine the target machine /// \param Triple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the /// either the target triple from the module, or the target triple of the
▲ Show 20 Lines • Show All 694 Lines • ▼ Show 20 Lines
/// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget); /// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
/// } /// }
template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo { template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo {
RegisterMCSubtargetInfo(Target &T) { RegisterMCSubtargetInfo(Target &T) {
TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
} }
private: private:
static MCSubtargetInfo *Allocator(StringRef /*TT*/, StringRef /*CPU*/, static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
StringRef /*FS*/) { StringRef /*FS*/) {
return new MCSubtargetInfoImpl(); return new MCSubtargetInfoImpl();
} }
}; };
/// RegisterMCSubtargetInfoFn - Helper template for registering a target /// RegisterMCSubtargetInfoFn - Helper template for registering a target
/// subtarget info implementation. This invokes the specified function to /// subtarget info implementation. This invokes the specified function to
/// do the construction. Usage: /// do the construction. Usage:
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

llvm/trunk/lib/MC/MCSubtargetInfo.cpp

Show All 28 Lines
void void
MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) { MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
if (!CPU.empty()) if (!CPU.empty())
CPUSchedModel = getSchedModelForCPU(CPU); CPUSchedModel = getSchedModelForCPU(CPU);
else else
CPUSchedModel = MCSchedModel::GetDefaultSchedModel(); CPUSchedModel = MCSchedModel::GetDefaultSchedModel();
} }
void void MCSubtargetInfo::InitMCSubtargetInfo(
MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, const Triple &TT, StringRef C, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
const SubtargetInfoKV *ProcSched, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const MCWriteProcResEntry *WPR, const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC,
const unsigned *FP) {
TargetTriple = TT; TargetTriple = TT;
CPU = C; CPU = C;
ProcFeatures = PF; ProcFeatures = PF;
ProcDesc = PD; ProcDesc = PD;
ProcSchedModels = ProcSched; ProcSchedModels = ProcSched;
WriteProcResTable = WPR; WriteProcResTable = WPR;
WriteLatencyTable = WL; WriteLatencyTable = WL;
ReadAdvanceTable = RA; ReadAdvanceTable = RA;
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

Show All 23 Lines
#include <string> #include <string>
#define GET_SUBTARGETINFO_HEADER #define GET_SUBTARGETINFO_HEADER
#include "AArch64GenSubtargetInfo.inc" #include "AArch64GenSubtargetInfo.inc"
namespace llvm { namespace llvm {
class GlobalValue; class GlobalValue;
class StringRef; class StringRef;
class Triple;
class AArch64Subtarget : public AArch64GenSubtargetInfo { class AArch64Subtarget : public AArch64GenSubtargetInfo {
protected: protected:
enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone}; enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others. /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
ARMProcFamilyEnum ARMProcFamily; ARMProcFamilyEnum ARMProcFamily;
Show All 26 Linesprivate:
/// initializeSubtargetDependencies - Initializes using CPUString and the /// initializeSubtargetDependencies - Initializes using CPUString and the
/// passed in feature string so that we can use initializer lists for /// passed in feature string so that we can use initializer lists for
/// subtarget initialization. /// subtarget initialization.
AArch64Subtarget &initializeSubtargetDependencies(StringRef FS); AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
AArch64Subtarget(const std::string &TT, const std::string &CPU, AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM, const std::string &FS, const TargetMachine &TM,
bool LittleEndian); bool LittleEndian);
const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override { const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
const AArch64FrameLowering *getFrameLowering() const override { const AArch64FrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

Show All 36 LinesAArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
if (CPUString.empty()) if (CPUString.empty())
CPUString = "generic"; CPUString = "generic";
ParseSubtargetFeatures(CPUString, FS); ParseSubtargetFeatures(CPUString, FS);
return *this; return *this;
} }
AArch64Subtarget::AArch64Subtarget(const std::string &TT, AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &CPU,
const std::string &FS, const std::string &FS,
const TargetMachine &TM, bool LittleEndian) const TargetMachine &TM, bool LittleEndian)
: AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
HasV8_1aOps(false), HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(), IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS)), InstrInfo(initializeSubtargetDependencies(FS)),
TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {} TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
/// ClassifyGlobalReference - Find the target operand flags that describe /// ClassifyGlobalReference - Find the target operand flags that describe
/// how a global value should be referenced for the current subtarget. /// how a global value should be referenced for the current subtarget.
unsigned char unsigned char
AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV, AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines std::string FS = !FSAttr.hasAttribute(Attribute::None)
: TargetFS; : TargetFS;
auto &I = SubtargetMap[CPU + FS]; auto &I = SubtargetMap[CPU + FS];
if (!I) { if (!I) {
// This needs to be done before we create a new subtarget since any // This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle); I = llvm::make_unique<AArch64Subtarget>(Triple(TargetTriple), CPU, FS,
*this, isLittle);
} }
return I.get(); return I.get();
} }
void AArch64leTargetMachine::anchor() { } void AArch64leTargetMachine::anchor() { }
AArch64leTargetMachine:: AArch64leTargetMachine::
AArch64leTargetMachine(const Target &T, StringRef TT, AArch64leTargetMachine(const Target &T, StringRef TT,
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Show All 35 Lines
static MCInstrInfo *createAArch64MCInstrInfo() { static MCInstrInfo *createAArch64MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitAArch64MCInstrInfo(X); InitAArch64MCInstrInfo(X);
return X; return X;
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
if (CPU.empty()) if (CPU.empty())
CPU = "generic"; CPU = "generic";
InitAArch64MCSubtargetInfo(X, TT, CPU, FS); InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Show First 20 Lines • Show All 558 Lines • ▼ Show 20 Linesvoid ARMAsmPrinter::emitAttributes() {
ATS.switchVendor("aeabi"); ATS.switchVendor("aeabi");
// Compute ARM ELF Attributes based on the default subtarget that // Compute ARM ELF Attributes based on the default subtarget that
// we'd have constructed. The existing ARM behavior isn't LTO clean // we'd have constructed. The existing ARM behavior isn't LTO clean
// anyhow. // anyhow.
// FIXME: For ifunc related functions we could iterate over and look // FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one. // for a feature string that doesn't match the default one.
StringRef TT = TM.getTargetTriple(); const Triple TT(TM.getTargetTriple());
StringRef CPU = TM.getTargetCPU(); StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
else else
ArchFS = FS; ArchFS = FS;
▲ Show 20 Lines • Show All 1,291 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Linesprotected:
const TargetOptions &Options; const TargetOptions &Options;
const ARMBaseTargetMachine &TM; const ARMBaseTargetMachine &TM;
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
ARMSubtarget(const std::string &TT, const std::string &CPU, ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle); const ARMBaseTargetMachine &TM, bool IsLittle);
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call. /// that still makes it profitable to inline the call.
unsigned getMaxInlineSizeThreshold() const { unsigned getMaxInlineSizeThreshold() const {
return 64; return 64;
} }
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
▲ Show 20 Lines • Show All 209 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 LinesARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
StringRef FS) { StringRef FS) {
ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS); ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
if (STI.isThumb1Only()) if (STI.isThumb1Only())
return (ARMFrameLowering *)new Thumb1FrameLowering(STI); return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
return new ARMFrameLowering(STI); return new ARMFrameLowering(STI);
} }
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const std::string &FS,
const ARMBaseTargetMachine &TM, bool IsLittle) const ARMBaseTargetMachine &TM, bool IsLittle)
: ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle), ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
TargetTriple(TT), Options(TM.Options), TM(TM), TargetTriple(TT), Options(TM.Options), TM(TM),
TSInfo(*TM.getDataLayout()), TSInfo(*TM.getDataLayout()),
FrameLowering(initializeFrameLowering(CPU, FS)), FrameLowering(initializeFrameLowering(CPU, FS)),
// At this point initializeSubtargetDependencies has been called so // At this point initializeSubtargetDependencies has been called so
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines if (isTargetDarwin() && TargetTriple.getArchName().endswith("v7s"))
CPUString = "swift"; CPUString = "swift";
else else
CPUString = "generic"; CPUString = "generic";
} }
// Insert the architecture feature derived from the target triple into the // Insert the architecture feature derived from the target triple into the
// feature string. This is important for setting features that are implied // feature string. This is important for setting features that are implied
// based on the architecture version. // based on the architecture version.
std::string ArchFS = std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
ARM_MC::ParseARMTriple(TargetTriple.getTriple(), CPUString);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
else else
ArchFS = FS; ArchFS = FS;
} }
ParseSubtargetFeatures(CPUString, ArchFS); ParseSubtargetFeatures(CPUString, ArchFS);
▲ Show 20 Lines • Show All 163 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 LinesARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, RM, CM, OL), CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)), TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) {
// Default to triple-appropriate float ABI // Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default) if (Options.FloatABIType == FloatABI::Default)
this->Options.FloatABIType = this->Options.FloatABIType =
Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft; Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
} }
ARMBaseTargetMachine::~ARMBaseTargetMachine() {} ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
Show All 24 Lines if (SoftFloat)
FS += FS.empty() ? "+soft-float" : ",+soft-float"; FS += FS.empty() ? "+soft-float" : ",+soft-float";
auto &I = SubtargetMap[CPU + FS]; auto &I = SubtargetMap[CPU + FS];
if (!I) { if (!I) {
// This needs to be done before we create a new subtarget since any // This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle); I = llvm::make_unique<ARMSubtarget>(Triple(TargetTriple), CPU, FS, *this,
isLittle);
} }
return I.get(); return I.get();
} }
TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() { TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
return TargetIRAnalysis( return TargetIRAnalysis(
[this](Function &F) { return TargetTransformInfo(ARMTTIImpl(this, F)); }); [this](Function &F) { return TargetTransformInfo(ARMTTIImpl(this, F)); });
} }
▲ Show 20 Lines • Show All 182 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

Show All 18 Lines
namespace { namespace {
class ARMAsmBackend : public MCAsmBackend { class ARMAsmBackend : public MCAsmBackend {
const MCSubtargetInfo *STI; const MCSubtargetInfo *STI;
bool isThumbMode; // Currently emitting Thumb code. bool isThumbMode; // Currently emitting Thumb code.
bool IsLittleEndian; // Big or little endian. bool IsLittleEndian; // Big or little endian.
public: public:
ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle) ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
: MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT.str(), "", "")), : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
isThumbMode(TT.getArchName().startswith("thumb")), isThumbMode(TT.getArchName().startswith("thumb")),
IsLittleEndian(IsLittle) {} IsLittleEndian(IsLittle) {}
~ARMAsmBackend() override { delete STI; } ~ARMAsmBackend() override { delete STI; }
unsigned getNumFixupKinds() const override { unsigned getNumFixupKinds() const override {
return ARM::NumTargetFixupKinds; return ARM::NumTargetFixupKinds;
} }
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llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

Show All 34 Lines
class Triple; class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
extern Target TheARMLETarget, TheThumbLETarget; extern Target TheARMLETarget, TheThumbLETarget;
extern Target TheARMBETarget, TheThumbBETarget; extern Target TheARMBETarget, TheThumbBETarget;
namespace ARM_MC { namespace ARM_MC {
std::string ParseARMTriple(StringRef TT, StringRef CPU); std::string ParseARMTriple(const Triple &TT, StringRef CPU);
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry. /// do not need to go through TargetRegistry.
MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS); StringRef FS);
} }
MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S, MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrint, MCInstPrinter *InstPrint,
bool isVerboseAsm); bool isVerboseAsm);
MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
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llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
} }
#define GET_INSTRINFO_MC_DESC #define GET_INSTRINFO_MC_DESC
#include "ARMGenInstrInfo.inc" #include "ARMGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "ARMGenSubtargetInfo.inc" #include "ARMGenSubtargetInfo.inc"
std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { bool isThumb =
Triple triple(TT); TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
bool isThumb = triple.getArch() == Triple::thumb ||
triple.getArch() == Triple::thumbeb;
bool NoCPU = CPU == "generic" || CPU.empty(); bool NoCPU = CPU == "generic" || CPU.empty();
std::string ARMArchFeature; std::string ARMArchFeature;
switch (triple.getSubArch()) { switch (TT.getSubArch()) {
default: default:
llvm_unreachable("invalid sub-architecture for ARM"); llvm_unreachable("invalid sub-architecture for ARM");
case Triple::ARMSubArch_v8: case Triple::ARMSubArch_v8:
if (NoCPU) if (NoCPU)
// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
// FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
// FeatureT2XtPk, FeatureCrypto, FeatureCRC // FeatureT2XtPk, FeatureCrypto, FeatureCRC
ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm," ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,"
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Linesstd::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
if (isThumb) { if (isThumb) {
if (ARMArchFeature.empty()) if (ARMArchFeature.empty())
ARMArchFeature = "+thumb-mode"; ARMArchFeature = "+thumb-mode";
else else
ARMArchFeature += ",+thumb-mode"; ARMArchFeature += ",+thumb-mode";
} }
if (triple.isOSNaCl()) { if (TT.isOSNaCl()) {
if (ARMArchFeature.empty()) if (ARMArchFeature.empty())
ARMArchFeature = "+nacl-trap"; ARMArchFeature = "+nacl-trap";
else else
ARMArchFeature += ",+nacl-trap"; ARMArchFeature += ",+nacl-trap";
} }
return ARMArchFeature; return ARMArchFeature;
} }
MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
else else
ArchFS = FS; ArchFS = FS;
} }
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llvm/trunk/lib/Target/BPF/BPFSubtarget.h

Show All 32 Linesclass BPFSubtarget : public BPFGenSubtargetInfo {
BPFInstrInfo InstrInfo; BPFInstrInfo InstrInfo;
BPFFrameLowering FrameLowering; BPFFrameLowering FrameLowering;
BPFTargetLowering TLInfo; BPFTargetLowering TLInfo;
TargetSelectionDAGInfo TSInfo; TargetSelectionDAGInfo TSInfo;
public: public:
// This constructor initializes the data members to match that // This constructor initializes the data members to match that
// of the specified triple. // of the specified triple.
BPFSubtarget(const std::string &TT, const std::string &CPU, BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const TargetMachine &TM); const TargetMachine &TM);
// ParseSubtargetFeatures - Parses features string setting specified // ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is auto generated by tblgen. // subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; } const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const BPFFrameLowering *getFrameLowering() const override { const BPFFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
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llvm/trunk/lib/Target/BPF/BPFSubtarget.cpp

Show All 19 Lines
#define DEBUG_TYPE "bpf-subtarget" #define DEBUG_TYPE "bpf-subtarget"
#define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR #define GET_SUBTARGETINFO_CTOR
#include "BPFGenSubtargetInfo.inc" #include "BPFGenSubtargetInfo.inc"
void BPFSubtarget::anchor() {} void BPFSubtarget::anchor() {}
BPFSubtarget::BPFSubtarget(const std::string &TT, const std::string &CPU, BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM) const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}

llvm/trunk/lib/Target/BPF/BPFTargetMachine.cpp

Show All 37 Lines
BPFTargetMachine::BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU, BPFTargetMachine::BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }
namespace { namespace {
// BPF Code Generator Pass Configuration Options. // BPF Code Generator Pass Configuration Options.
class BPFPassConfig : public TargetPassConfig { class BPFPassConfig : public TargetPassConfig {
public: public:
BPFPassConfig(BPFTargetMachine *TM, PassManagerBase &PM) BPFPassConfig(BPFTargetMachine *TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {} : TargetPassConfig(TM, PM) {}
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llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

Show All 40 Lines
} }
static MCRegisterInfo *createBPFMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createBPFMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */); InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */);
return X; return X;
} }
static MCSubtargetInfo *createBPFMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitBPFMCSubtargetInfo(X, TT, CPU, FS); InitBPFMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCCodeGenInfo *createBPFMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createBPFMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OL) { CodeGenOpt::Level OL) {
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llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesprivate:
std::string CPUString; std::string CPUString;
HexagonInstrInfo InstrInfo; HexagonInstrInfo InstrInfo;
HexagonTargetLowering TLInfo; HexagonTargetLowering TLInfo;
HexagonSelectionDAGInfo TSInfo; HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering; HexagonFrameLowering FrameLowering;
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
public: public:
HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM); const TargetMachine &TM);
/// getInstrItins - Return the instruction itineraries based on subtarget /// getInstrItins - Return the instruction itineraries based on subtarget
/// selection. /// selection.
const InstrItineraryData *getInstrItineraryData() const override { const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins; return &InstrItins;
} }
const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 LinesHexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
} else { } else {
llvm_unreachable("Unrecognized Hexagon processor version"); llvm_unreachable("Unrecognized Hexagon processor version");
} }
ParseSubtargetFeatures(CPUString, FS); ParseSubtargetFeatures(CPUString, FS);
return *this; return *this;
} }
HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
const TargetMachine &TM) StringRef FS, const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()), FrameLowering() { TSInfo(*TM.getDataLayout()), FrameLowering() {
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString); InstrItins = getInstrItineraryForCPU(CPUString);
// UseMemOps on by default unless disabled explicitly // UseMemOps on by default unless disabled explicitly
Show All 21 Lines

llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS, : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()), TLOF(make_unique<HexagonTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }
HexagonTargetMachine::~HexagonTargetMachine() {} HexagonTargetMachine::~HexagonTargetMachine() {}
namespace { namespace {
/// Hexagon Code Generator Pass Configuration Options. /// Hexagon Code Generator Pass Configuration Options.
class HexagonPassConfig : public TargetPassConfig { class HexagonPassConfig : public TargetPassConfig {
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llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitHexagonMCRegisterInfo(X, Hexagon::R0); InitHexagonMCRegisterInfo(X, Hexagon::R0);
return X; return X;
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitHexagonMCSubtargetInfo(X, TT, CPU, FS); InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) { const Triple &TT) {
MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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llvm/trunk/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

Show All 37 Lines
} }
static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) { static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitMSP430MCRegisterInfo(X, MSP430::PC); InitMSP430MCRegisterInfo(X, MSP430::PC);
return X; return X;
} }
static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitMSP430MCSubtargetInfo(X, TT, CPU, FS); InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OL) { CodeGenOpt::Level OL) {
Show All 38 Lines

llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h

Show All 35 Linesclass MSP430Subtarget : public MSP430GenSubtargetInfo {
MSP430InstrInfo InstrInfo; MSP430InstrInfo InstrInfo;
MSP430TargetLowering TLInfo; MSP430TargetLowering TLInfo;
MSP430SelectionDAGInfo TSInfo; MSP430SelectionDAGInfo TSInfo;
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
MSP430Subtarget(const std::string &TT, const std::string &CPU, MSP430Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM); const std::string &FS, const TargetMachine &TM);
MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
Show All 17 Lines

llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp

Show All 25 Lines
void MSP430Subtarget::anchor() { } void MSP430Subtarget::anchor() { }
MSP430Subtarget & MSP430Subtarget &
MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
ParseSubtargetFeatures("generic", FS); ParseSubtargetFeatures("generic", FS);
return *this; return *this;
} }
MSP430Subtarget::MSP430Subtarget(const std::string &TT, const std::string &CPU, MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM) const std::string &FS, const TargetMachine &TM)
: MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()) {} TSInfo(*TM.getDataLayout()) {}

llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp

Show All 28 LinesMSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, "e-m:e-p:16:16-i32:16:32-a:16-n8:16", TT, CPU, FS, : LLVMTargetMachine(T, "e-m:e-p:16:16-i32:16:32-a:16-n8:16", TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
// FIXME: Check DataLayout string. // FIXME: Check DataLayout string.
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }
MSP430TargetMachine::~MSP430TargetMachine() {} MSP430TargetMachine::~MSP430TargetMachine() {}
namespace { namespace {
/// MSP430 Code Generator Pass Configuration Options. /// MSP430 Code Generator Pass Configuration Options.
class MSP430PassConfig : public TargetPassConfig { class MSP430PassConfig : public TargetPassConfig {
Show All 27 Lines

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
MCAsmBackend *createMipsAsmBackendEL64(const Target &T, MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
bool IsLittleEndian, bool Is64Bit); bool IsLittleEndian, bool Is64Bit);
namespace MIPS_MC { namespace MIPS_MC {
StringRef selectMipsCPU(StringRef TT, StringRef CPU); StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
} }
} // End llvm namespace } // End llvm namespace
// Defines symbolic names for Mips registers. This defines a mapping from // Defines symbolic names for Mips registers. This defines a mapping from
// register name to register number. // register name to register number.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc" #include "MipsGenRegisterInfo.inc"
Show All 9 Lines

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

Show All 37 Lines
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "MipsGenSubtargetInfo.inc" #include "MipsGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "MipsGenRegisterInfo.inc" #include "MipsGenRegisterInfo.inc"
/// Select the Mips CPU for the given triple and cpu name. /// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsSubtarget.cpp /// FIXME: Merge with the copy in MipsSubtarget.cpp
StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) { StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
if (CPU.empty() || CPU == "generic") { if (CPU.empty() || CPU == "generic") {
Triple TheTriple(TT); if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
if (TheTriple.getArch() == Triple::mips ||
TheTriple.getArch() == Triple::mipsel)
CPU = "mips32"; CPU = "mips32";
else else
CPU = "mips64"; CPU = "mips64";
} }
return CPU; return CPU;
} }
static MCInstrInfo *createMipsMCInstrInfo() { static MCInstrInfo *createMipsMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitMipsMCInstrInfo(X); InitMipsMCInstrInfo(X);
return X; return X;
} }
static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitMipsMCRegisterInfo(X, Mips::RA); InitMipsMCRegisterInfo(X, Mips::RA);
return X; return X;
} }
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
CPU = MIPS_MC::selectMipsCPU(TT, CPU); CPU = MIPS_MC::selectMipsCPU(TT, CPU);
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS); InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) { const Triple &TT) {
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp

Show First 20 Lines • Show All 688 Lines • ▼ Show 20 Lines
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// Compute MIPS architecture attributes based on the default subtarget // Compute MIPS architecture attributes based on the default subtarget
// that we'd have constructed. Module level directives aren't LTO // that we'd have constructed. Module level directives aren't LTO
// clean anyhow. // clean anyhow.
// FIXME: For ifunc related functions we could iterate over and look // FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one. // for a feature string that doesn't match the default one.
StringRef TT = TM.getTargetTriple(); const Triple TT(TM.getTargetTriple());
StringRef CPU = StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
MIPS_MC::selectMipsCPU(TM.getTargetTriple(), TM.getTargetCPU());
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM); const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
bool IsABICalls = STI.isABICalls(); bool IsABICalls = STI.isABICalls();
const MipsABIInfo &ABI = MTM.getABI(); const MipsABIInfo &ABI = MTM.getABI();
if (IsABICalls) { if (IsABICalls) {
getTargetStreamer().emitDirectiveAbiCalls(); getTargetStreamer().emitDirectiveAbiCalls();
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llvm/trunk/lib/Target/Mips/MipsSubtarget.h

Show First 20 Lines • Show All 155 Lines • ▼ Show 20 Linespublic:
bool isABI_N64() const; bool isABI_N64() const;
bool isABI_N32() const; bool isABI_N32() const;
bool isABI_O32() const; bool isABI_O32() const;
const MipsABIInfo &getABI() const; const MipsABIInfo &getABI() const;
bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, bool little, bool little, const MipsTargetMachine &TM);
const MipsTargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool hasMips1() const { return MipsArchVersion >= Mips1; } bool hasMips1() const { return MipsArchVersion >= Mips1; }
bool hasMips2() const { return MipsArchVersion >= Mips2; } bool hasMips2() const { return MipsArchVersion >= Mips2; }
bool hasMips3() const { return MipsArchVersion >= Mips3; } bool hasMips3() const { return MipsArchVersion >= Mips3; }
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llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
cl::init(true)); cl::init(true));
static cl::opt<bool> static cl::opt<bool>
GPOpt("mgpopt", cl::Hidden, GPOpt("mgpopt", cl::Hidden,
cl::desc("Enable gp-relative addressing of mips small data items")); cl::desc("Enable gp-relative addressing of mips small data items"));
void MipsSubtarget::anchor() { } void MipsSubtarget::anchor() { }
MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, bool little, const std::string &FS, bool little,
const MipsTargetMachine &TM) const MipsTargetMachine &TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
return CodeGenOpt::Aggressive; return CodeGenOpt::Aggressive;
} }
MipsSubtarget & MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM) { const TargetMachine &TM) {
std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); std::string CPUName =
MIPS_MC::selectMipsCPU(Triple(TM.getTargetTriple()), CPU);
// Parse features string. // Parse features string.
ParseSubtargetFeatures(CPUName, FS); ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName); InstrItins = getInstrItineraryForCPU(CPUName);
if (InMips16Mode && !IsSoftFloat) if (InMips16Mode && !IsSoftFloat)
InMips16HardFloat = true; InMips16HardFloat = true;
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llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 LinesMipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, RM, CM, OL), CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()), isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)), ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), Subtarget(nullptr),
NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", DefaultSubtarget(Triple(TT), CPU, FS, isLittle, *this),
NoMips16Subtarget(Triple(TT), CPU,
FS.empty() ? "-mips16" : FS.str() + ",-mips16",
isLittle, *this), isLittle, *this),
Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", Mips16Subtarget(Triple(TT), CPU,
isLittle, *this) { FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle,
*this) {
Subtarget = &DefaultSubtarget; Subtarget = &DefaultSubtarget;
initAsmInfo(); initAsmInfo();
} }
MipsTargetMachine::~MipsTargetMachine() {} MipsTargetMachine::~MipsTargetMachine() {}
void MipsebTargetMachine::anchor() { } void MipsebTargetMachine::anchor() { }
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FS += FS.empty() ? "+soft-float" : ",+soft-float"; FS += FS.empty() ? "+soft-float" : ",+soft-float";
auto &I = SubtargetMap[CPU + FS]; auto &I = SubtargetMap[CPU + FS];
if (!I) { if (!I) {
// This needs to be done before we create a new subtarget since any // This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this); I = llvm::make_unique<MipsSubtarget>(Triple(TargetTriple), CPU, FS,
isLittle, *this);
} }
return I.get(); return I.get();
} }
void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
DEBUG(dbgs() << "resetSubtarget\n"); DEBUG(dbgs() << "resetSubtarget\n");
Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction())); Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
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llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

Show All 39 Lines
static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
// PTX does not have a return address register. // PTX does not have a return address register.
InitNVPTXMCRegisterInfo(X, 0); InitNVPTXMCRegisterInfo(X, 0);
return X; return X;
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitNVPTXMCSubtargetInfo(X, TT, CPU, FS); InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCCodeGenInfo *createNVPTXMCCodeGenInfo( static MCCodeGenInfo *createNVPTXMCCodeGenInfo(
StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo(); MCCodeGenInfo *X = new MCCodeGenInfo();
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llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp

Show First 20 Lines • Show All 802 Lines • ▼ Show 20 Lines for (DISubprogram *SP : DbgFinder.subprograms()) {
++i; ++i;
} }
} }
bool NVPTXAsmPrinter::doInitialization(Module &M) { bool NVPTXAsmPrinter::doInitialization(Module &M) {
// Construct a default subtarget off of the TargetMachine defaults. The // Construct a default subtarget off of the TargetMachine defaults. The
// rest of NVPTX isn't friendly to change subtargets per function and // rest of NVPTX isn't friendly to change subtargets per function and
// so the default TargetMachine will have all of the options. // so the default TargetMachine will have all of the options.
StringRef TT = TM.getTargetTriple(); const Triple TT(TM.getTargetTriple());
StringRef CPU = TM.getTargetCPU(); StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString(); StringRef FS = TM.getTargetFeatureString();
const NVPTXTargetMachine &NTM = static_cast<const NVPTXTargetMachine &>(TM); const NVPTXTargetMachine &NTM = static_cast<const NVPTXTargetMachine &>(TM);
const NVPTXSubtarget STI(TT, CPU, FS, NTM); const NVPTXSubtarget STI(TT, CPU, FS, NTM);
SmallString<128> Str1; SmallString<128> Str1;
raw_svector_ostream OS1(Str1); raw_svector_ostream OS1(Str1);
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llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesclass NVPTXSubtarget : public NVPTXGenSubtargetInfo {
// NVPTX does not have any call stack frame, but need a NVPTX specific // NVPTX does not have any call stack frame, but need a NVPTX specific
// FrameLowering class because TargetFrameLowering is abstract. // FrameLowering class because TargetFrameLowering is abstract.
NVPTXFrameLowering FrameLowering; NVPTXFrameLowering FrameLowering;
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified module. /// of the specified module.
/// ///
NVPTXSubtarget(const std::string &TT, const std::string &CPU, NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const NVPTXTargetMachine &TM); const std::string &FS, const NVPTXTargetMachine &TM);
const TargetFrameLowering *getFrameLowering() const override { const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; } const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const NVPTXRegisterInfo *getRegisterInfo() const override { const NVPTXRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
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llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp

Show All 37 LinesNVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
// Set default to PTX 3.2 (CUDA 5.5) // Set default to PTX 3.2 (CUDA 5.5)
if (PTXVersion == 0) { if (PTXVersion == 0) {
PTXVersion = 32; PTXVersion = 32;
} }
return *this; return *this;
} }
NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const std::string &FS,
const NVPTXTargetMachine &TM) const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM),
InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
TSInfo(TM.getDataLayout()), FrameLowering() {} TSInfo(TM.getDataLayout()), FrameLowering() {}
bool NVPTXSubtarget::hasImageHandles() const { bool NVPTXSubtarget::hasImageHandles() const {
// Enable handles for Kepler+, where CUDA supports indirect surfaces and // Enable handles for Kepler+, where CUDA supports indirect surfaces and
// textures // textures
if (TM.getDrvInterface() == NVPTX::CUDA) if (TM.getDrvInterface() == NVPTX::CUDA)
return (SmVersion >= 30); return (SmVersion >= 30);
// Disabled, otherwise // Disabled, otherwise
return false; return false;
} }

llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT, NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit) CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
CM, OL), CM, OL),
is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()), is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
if (Triple(TT).getOS() == Triple::NVCL) if (Triple(TT).getOS() == Triple::NVCL)
drvInterface = NVPTX::NVCL; drvInterface = NVPTX::NVCL;
else else
drvInterface = NVPTX::CUDA; drvInterface = NVPTX::CUDA;
initAsmInfo(); initAsmInfo();
} }
NVPTXTargetMachine::~NVPTXTargetMachine() {} NVPTXTargetMachine::~NVPTXTargetMachine() {}
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llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesstatic MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
unsigned Flavour = isPPC64 ? 0 : 1; unsigned Flavour = isPPC64 ? 0 : 1;
unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitPPCMCRegisterInfo(X, RA, Flavour, Flavour); InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
return X; return X;
} }
static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitPPCMCSubtargetInfo(X, TT, CPU, FS); InitPPCMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TheTriple) { const Triple &TheTriple) {
bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
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llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Linesprotected:
PPCInstrInfo InstrInfo; PPCInstrInfo InstrInfo;
PPCTargetLowering TLInfo; PPCTargetLowering TLInfo;
PPCSelectionDAGInfo TSInfo; PPCSelectionDAGInfo TSInfo;
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
PPCSubtarget(const std::string &TT, const std::string &CPU, PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const PPCTargetMachine &TM); const PPCTargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// getStackAlignment - Returns the minimum alignment known to hold of the /// getStackAlignment - Returns the minimum alignment known to hold of the
/// stack frame on entry to the function and which must be maintained by every /// stack frame on entry to the function and which must be maintained by every
/// function for this subtarget. /// function for this subtarget.
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llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) { StringRef FS) {
initializeEnvironment(); initializeEnvironment();
initSubtargetFeatures(CPU, FS); initSubtargetFeatures(CPU, FS);
return *this; return *this;
} }
PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const PPCTargetMachine &TM) const std::string &FS, const PPCTargetMachine &TM)
: PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
IsPPC64(TargetTriple.getArch() == Triple::ppc64 || IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
TargetTriple.getArch() == Triple::ppc64le), TargetTriple.getArch() == Triple::ppc64le),
TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {} InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
void PPCSubtarget::initializeEnvironment() { void PPCSubtarget::initializeEnvironment() {
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llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 LinesPPCTargetMachine::getSubtargetImpl(const Function &F) const {
auto &I = SubtargetMap[CPU + FS]; auto &I = SubtargetMap[CPU + FS];
if (!I) { if (!I) {
// This needs to be done before we create a new subtarget since any // This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<PPCSubtarget>( I = llvm::make_unique<PPCSubtarget>(
TargetTriple, CPU, Triple(TargetTriple), CPU,
// FIXME: It would be good to have the subtarget additions here // FIXME: It would be good to have the subtarget additions here
// not necessary. Anything that turns them on/off (overrides) ends // not necessary. Anything that turns them on/off (overrides) ends
// up being put at the end of the feature string, but the defaults // up being put at the end of the feature string, but the defaults
// shouldn't require adding them. Fixing this means pulling Feature64Bit // shouldn't require adding them. Fixing this means pulling Feature64Bit
// out of most of the target cpus in the .td file and making it set only // out of most of the target cpus in the .td file and making it set only
// as part of initialization via the TargetTriple. // as part of initialization via the TargetTriple.
computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this); computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
} }
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llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linesprivate:
AMDGPUFrameLowering FrameLowering; AMDGPUFrameLowering FrameLowering;
std::unique_ptr<AMDGPUTargetLowering> TLInfo; std::unique_ptr<AMDGPUTargetLowering> TLInfo;
std::unique_ptr<AMDGPUInstrInfo> InstrInfo; std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
InstrItineraryData InstrItins; InstrItineraryData InstrItins;
Triple TargetTriple; Triple TargetTriple;
public: public:
AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM); AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU, TargetMachine &TM);
StringRef FS); AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
StringRef GPU, StringRef FS);
const AMDGPUFrameLowering *getFrameLowering() const override { const AMDGPUFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
const AMDGPUInstrInfo *getInstrInfo() const override { const AMDGPUInstrInfo *getInstrInfo() const override {
return InstrInfo.get(); return InstrInfo.get();
} }
const AMDGPURegisterInfo *getRegisterInfo() const override { const AMDGPURegisterInfo *getRegisterInfo() const override {
▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/R600/AMDGPUSubtarget.cpp

Show All 26 Lines
#define DEBUG_TYPE "amdgpu-subtarget" #define DEBUG_TYPE "amdgpu-subtarget"
#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR #define GET_SUBTARGETINFO_CTOR
#include "AMDGPUGenSubtargetInfo.inc" #include "AMDGPUGenSubtargetInfo.inc"
AMDGPUSubtarget & AMDGPUSubtarget &
AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU, AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
StringRef FS) { StringRef GPU, StringRef FS) {
// Determine default and user-specified characteristics // Determine default and user-specified characteristics
// On SI+, we want FP64 denormals to be on by default. FP32 denormals can be // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
// enabled, but some instructions do not respect them and they run at the // enabled, but some instructions do not respect them and they run at the
// double precision rate, so don't enable by default. // double precision rate, so don't enable by default.
// //
// We want to be able to turn these off, but making this a subtarget feature // We want to be able to turn these off, but making this a subtarget feature
// for SI has the unhelpful behavior that it unsets everything else if you // for SI has the unhelpful behavior that it unsets everything else if you
// disable it. // disable it.
SmallString<256> FullFS("+promote-alloca,+fp64-denormals,"); SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
FullFS += FS; FullFS += FS;
if (GPU == "" && Triple(TT).getArch() == Triple::amdgcn) if (GPU == "" && TT.getArch() == Triple::amdgcn)
GPU = "SI"; GPU = "SI";
ParseSubtargetFeatures(GPU, FullFS); ParseSubtargetFeatures(GPU, FullFS);
// FIXME: I don't think think Evergreen has any useful support for // FIXME: I don't think think Evergreen has any useful support for
// denormals, but should be checked. Should we issue a warning somewhere // denormals, but should be checked. Should we issue a warning somewhere
// if someone tries to enable these? // if someone tries to enable these?
if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
FP32Denormals = false; FP32Denormals = false;
FP64Denormals = false; FP64Denormals = false;
} }
return *this; return *this;
} }
AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
TargetMachine &TM) TargetMachine &TM)
: AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
DumpCode(false), R600ALUInst(false), HasVertexCache(false), DumpCode(false), R600ALUInst(false), HasVertexCache(false),
TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false), TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
FP64Denormals(false), FP32Denormals(false), FastFMAF32(false), FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true), CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false), EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
WavefrontSize(0), CFALUBug(false), LocalMemorySize(0), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
EnableVGPRSpilling(false), SGPRInitBug(false), EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
LDSBankCount(0),
FrameLowering(TargetFrameLowering::StackGrowsUp, FrameLowering(TargetFrameLowering::StackGrowsUp,
64 * 16, // Maximum stack alignment (long16) 64 * 16, // Maximum stack alignment (long16)
0), 0),
InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) { InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
initializeSubtargetDependencies(TT, GPU, FS); initializeSubtargetDependencies(TT, GPU, FS);
if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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llvm/trunk/lib/Target/R600/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OptLevel) CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
OptLevel), OptLevel),
TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this), TLOF(new TargetLoweringObjectFileELF()),
IntrinsicInfo() { Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() {
setRequiresStructuredCFG(true); setRequiresStructuredCFG(true);
initAsmInfo(); initAsmInfo();
} }
AMDGPUTargetMachine::~AMDGPUTargetMachine() { AMDGPUTargetMachine::~AMDGPUTargetMachine() {
delete TLOF; delete TLOF;
} }
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llvm/trunk/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
} }
static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitAMDGPUMCRegisterInfo(X, 0); InitAMDGPUMCRegisterInfo(X, 0);
return X; return X;
} }
static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo * X = new MCSubtargetInfo(); MCSubtargetInfo * X = new MCSubtargetInfo();
InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS); InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OL) { CodeGenOpt::Level OL) {
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llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines#include "SparcGenAsmMatcher.inc"
// returns true if Tok is matched to a register and returns register in RegNo. // returns true if Tok is matched to a register and returns register in RegNo.
bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
unsigned &RegKind); unsigned &RegKind);
bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc); bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
bool parseDirectiveWord(unsigned Size, SMLoc L); bool parseDirectiveWord(unsigned Size, SMLoc L);
bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); } bool is64Bit() const {
return STI.getTargetTriple().getArchName().startswith("sparcv9");
}
void expandSET(MCInst &Inst, SMLoc IDLoc, void expandSET(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
public: public:
SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser, SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCTargetOptions &Options) const MCTargetOptions &Options)
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llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

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} }
static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitSparcMCRegisterInfo(X, SP::O7); InitSparcMCRegisterInfo(X, SP::O7);
return X; return X;
} }
static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
Triple TheTriple(TT);
if (CPU.empty()) if (CPU.empty())
CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8"; CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
InitSparcMCSubtargetInfo(X, TT, CPU, FS); InitSparcMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
// Code models. Some only make sense for 64-bit code. // Code models. Some only make sense for 64-bit code.
// //
// SunCC Reloc CodeModel Constraints // SunCC Reloc CodeModel Constraints
// abs32 Static Small text+data+bss linked below 2^32 bytes // abs32 Static Small text+data+bss linked below 2^32 bytes
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llvm/trunk/lib/Target/Sparc/SparcSubtarget.h

Show All 37 Linesclass SparcSubtarget : public SparcGenSubtargetInfo {
bool HasHardQuad; bool HasHardQuad;
bool UsePopc; bool UsePopc;
SparcInstrInfo InstrInfo; SparcInstrInfo InstrInfo;
SparcTargetLowering TLInfo; SparcTargetLowering TLInfo;
SparcSelectionDAGInfo TSInfo; SparcSelectionDAGInfo TSInfo;
SparcFrameLowering FrameLowering; SparcFrameLowering FrameLowering;
public: public:
SparcSubtarget(const std::string &TT, const std::string &CPU, SparcSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, TargetMachine &TM, bool is64bit); const std::string &FS, TargetMachine &TM, bool is64bit);
const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const TargetFrameLowering *getFrameLowering() const override { const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
const SparcRegisterInfo *getRegisterInfo() const override { const SparcRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
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llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 LinesSparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
// Popc is a v9-only instruction. // Popc is a v9-only instruction.
if (!IsV9) if (!IsV9)
UsePopc = false; UsePopc = false;
return *this; return *this;
} }
SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, TargetMachine &TM, const std::string &FS, TargetMachine &TM,
bool is64Bit) bool is64Bit)
: SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()), FrameLowering(*this) {} TSInfo(*TM.getDataLayout()), FrameLowering(*this) {}
int SparcSubtarget::getAdjustedFrameSize(int frameSize) const { int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
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llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp

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SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit) CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()), TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this, is64bit) { Subtarget(Triple(TT), CPU, FS, *this, is64bit) {
initAsmInfo(); initAsmInfo();
} }
SparcTargetMachine::~SparcTargetMachine() {} SparcTargetMachine::~SparcTargetMachine() {}
namespace { namespace {
/// Sparc Code Generator Pass Configuration Options. /// Sparc Code Generator Pass Configuration Options.
class SparcPassConfig : public TargetPassConfig { class SparcPassConfig : public TargetPassConfig {
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llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
} }
static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createSystemZMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitSystemZMCRegisterInfo(X, SystemZ::R14D); InitSystemZMCRegisterInfo(X, SystemZ::R14D);
return X; return X;
} }
static MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, static MCSubtargetInfo *
StringRef CPU, createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitSystemZMCSubtargetInfo(X, TT, CPU, FS); InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OL) { CodeGenOpt::Level OL) {
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llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesprivate:
SystemZInstrInfo InstrInfo; SystemZInstrInfo InstrInfo;
SystemZTargetLowering TLInfo; SystemZTargetLowering TLInfo;
SystemZSelectionDAGInfo TSInfo; SystemZSelectionDAGInfo TSInfo;
SystemZFrameLowering FrameLowering; SystemZFrameLowering FrameLowering;
SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU, SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU,
StringRef FS); StringRef FS);
public: public:
SystemZSubtarget(const std::string &TT, const std::string &CPU, SystemZSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM); const std::string &FS, const TargetMachine &TM);
const TargetFrameLowering *getFrameLowering() const override { const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
const SystemZInstrInfo *getInstrInfo() const override { return &InstrInfo; } const SystemZInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const SystemZRegisterInfo *getRegisterInfo() const override { const SystemZRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
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llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp

Show All 26 LinesSystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
std::string CPUName = CPU; std::string CPUName = CPU;
if (CPUName.empty()) if (CPUName.empty())
CPUName = "generic"; CPUName = "generic";
// Parse features string. // Parse features string.
ParseSubtargetFeatures(CPUName, FS); ParseSubtargetFeatures(CPUName, FS);
return *this; return *this;
} }
SystemZSubtarget::SystemZSubtarget(const std::string &TT, SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
const std::string &CPU,
const std::string &FS, const std::string &FS,
const TargetMachine &TM) const TargetMachine &TM)
: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
HasPopulationCount(false), HasFastSerialization(false), HasPopulationCount(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
HasTransactionalExecution(false), HasProcessorAssist(false), HasTransactionalExecution(false), HasProcessorAssist(false),
HasVector(false), HasVector(false), TargetTriple(TT),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {} TSInfo(*TM.getDataLayout()), FrameLowering() {}
// Return true if GV binds locally under reloc model RM. // Return true if GV binds locally under reloc model RM.
static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) { static bool bindsLocally(const GlobalValue *GV, Reloc::Model RM) {
// For non-PIC, all symbols bind locally. // For non-PIC, all symbols bind locally.
if (RM == Reloc::Static) if (RM == Reloc::Static)
return true; return true;
return GV->hasLocalLinkage() || !GV->hasDefaultVisibility(); return GV->hasLocalLinkage() || !GV->hasDefaultVisibility();
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llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesstatic std::string computeDataLayout(StringRef TT, StringRef CPU,
return Ret; return Ret;
} }
SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
TT, CPU, FS, Options, RM, CM, OL), RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }
SystemZTargetMachine::~SystemZTargetMachine() {} SystemZTargetMachine::~SystemZTargetMachine() {}
namespace { namespace {
/// SystemZ Code Generator Pass Configuration Options. /// SystemZ Code Generator Pass Configuration Options.
class SystemZPassConfig : public TargetPassConfig { class SystemZPassConfig : public TargetPassConfig {
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llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
/// ///
namespace N86 { namespace N86 {
enum { enum {
EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
}; };
} }
namespace X86_MC { namespace X86_MC {
std::string ParseX86Triple(StringRef TT); std::string ParseX86Triple(const Triple &TT);
unsigned getDwarfRegFlavour(Triple TT, bool isEH); unsigned getDwarfRegFlavour(Triple TT, bool isEH);
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
/// do not need to go through TargetRegistry. /// do not need to go through TargetRegistry.
MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS); StringRef FS);
} }
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU); const Triple &TT, StringRef CPU);
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llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

Show All 36 Lines
#include "X86GenRegisterInfo.inc" #include "X86GenRegisterInfo.inc"
#define GET_INSTRINFO_MC_DESC #define GET_INSTRINFO_MC_DESC
#include "X86GenInstrInfo.inc" #include "X86GenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "X86GenSubtargetInfo.inc" #include "X86GenSubtargetInfo.inc"
std::string X86_MC::ParseX86Triple(StringRef TT) { std::string X86_MC::ParseX86Triple(const Triple &TT) {
Triple TheTriple(TT);
std::string FS; std::string FS;
if (TheTriple.getArch() == Triple::x86_64) if (TT.getArch() == Triple::x86_64)
FS = "+64bit-mode,-32bit-mode,-16bit-mode"; FS = "+64bit-mode,-32bit-mode,-16bit-mode";
else if (TheTriple.getEnvironment() != Triple::CODE16) else if (TT.getEnvironment() != Triple::CODE16)
FS = "-64bit-mode,+32bit-mode,-16bit-mode"; FS = "-64bit-mode,+32bit-mode,-16bit-mode";
else else
FS = "-64bit-mode,-32bit-mode,+16bit-mode"; FS = "-64bit-mode,-32bit-mode,+16bit-mode";
return FS; return FS;
} }
unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) { unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
Show All 11 Lines
void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
// FIXME: TableGen these. // FIXME: TableGen these.
for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
unsigned SEH = MRI->getEncodingValue(Reg); unsigned SEH = MRI->getEncodingValue(Reg);
MRI->mapLLVMRegToSEHReg(Reg, SEH); MRI->mapLLVMRegToSEHReg(Reg, SEH);
} }
} }
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU, MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
StringRef FS) { StringRef CPU, StringRef FS) {
std::string ArchFS = X86_MC::ParseX86Triple(TT); std::string ArchFS = X86_MC::ParseX86Triple(TT);
if (!FS.empty()) { if (!FS.empty()) {
if (!ArchFS.empty()) if (!ArchFS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
else else
ArchFS = FS; ArchFS = FS;
} }
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llvm/trunk/lib/Target/X86/X86Subtarget.h

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Linesprivate:
X86InstrInfo InstrInfo; X86InstrInfo InstrInfo;
X86TargetLowering TLInfo; X86TargetLowering TLInfo;
X86FrameLowering FrameLowering; X86FrameLowering FrameLowering;
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
X86Subtarget(const std::string &TT, const std::string &CPU, X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const std::string &FS, const X86TargetMachine &TM, const X86TargetMachine &TM, unsigned StackAlignOverride);
unsigned StackAlignOverride);
const X86TargetLowering *getTargetLowering() const override { const X86TargetLowering *getTargetLowering() const override {
return &TLInfo; return &TLInfo;
} }
const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
const X86FrameLowering *getFrameLowering() const override { const X86FrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
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llvm/trunk/lib/Target/X86/X86Subtarget.cpp

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X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU, X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) { StringRef FS) {
initializeEnvironment(); initializeEnvironment();
initSubtargetFeatures(CPU, FS); initSubtargetFeatures(CPU, FS);
return *this; return *this;
} }
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const X86TargetMachine &TM, const std::string &FS, const X86TargetMachine &TM,
unsigned StackAlignOverride) unsigned StackAlignOverride)
: X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others), : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
PICStyle(PICStyles::None), TargetTriple(TT), PICStyle(PICStyles::None), TargetTriple(TT),
StackAlignOverride(StackAlignOverride), StackAlignOverride(StackAlignOverride),
In64BitMode(TargetTriple.getArch() == Triple::x86_64), In64BitMode(TargetTriple.getArch() == Triple::x86_64),
In32BitMode(TargetTriple.getArch() == Triple::x86 && In32BitMode(TargetTriple.getArch() == Triple::x86 &&
TargetTriple.getEnvironment() != Triple::CODE16), TargetTriple.getEnvironment() != Triple::CODE16),
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llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
/// ///
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options, : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
RM, CM, OL), RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) { Subtarget(Triple(TT), CPU, FS, *this, Options.StackAlignmentOverride) {
// Windows stack unwinder gets confused when execution flow "falls through" // Windows stack unwinder gets confused when execution flow "falls through"
// after a call to 'noreturn' function. // after a call to 'noreturn' function.
// To prevent that, we emit a trap for 'unreachable' IR instructions. // To prevent that, we emit a trap for 'unreachable' IR instructions.
// (which on X86, happens to be the 'ud2' instruction) // (which on X86, happens to be the 'ud2' instruction)
if (Subtarget.isTargetWin64()) if (Subtarget.isTargetWin64())
this->Options.TrapUnreachable = true; this->Options.TrapUnreachable = true;
// TODO: By default, all reciprocal estimate operations are off because // TODO: By default, all reciprocal estimate operations are off because
Show All 34 Lines if (SoftFloat)
FS += FS.empty() ? "+soft-float" : ",+soft-float"; FS += FS.empty() ? "+soft-float" : ",+soft-float";
auto &I = SubtargetMap[CPU + FS]; auto &I = SubtargetMap[CPU + FS];
if (!I) { if (!I) {
// This needs to be done before we create a new subtarget since any // This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the // creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions. // function that reside in TargetOptions.
resetTargetOptions(F); resetTargetOptions(F);
I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this, I = llvm::make_unique<X86Subtarget>(Triple(TargetTriple), CPU, FS, *this,
Options.StackAlignmentOverride); Options.StackAlignmentOverride);
} }
return I.get(); return I.get();
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Command line options for x86 // Command line options for x86
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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llvm/trunk/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

Show All 40 Lines
} }
static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) { static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitXCoreMCRegisterInfo(X, XCore::LR); InitXCoreMCRegisterInfo(X, XCore::LR);
return X; return X;
} }
static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *
StringRef FS) { createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitXCoreMCSubtargetInfo(X, TT, CPU, FS); InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;
} }
static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) { const Triple &TT) {
MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
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llvm/trunk/lib/Target/XCore/XCoreSubtarget.h

Show All 34 Linesclass XCoreSubtarget : public XCoreGenSubtargetInfo {
XCoreFrameLowering FrameLowering; XCoreFrameLowering FrameLowering;
XCoreTargetLowering TLInfo; XCoreTargetLowering TLInfo;
XCoreSelectionDAGInfo TSInfo; XCoreSelectionDAGInfo TSInfo;
public: public:
/// This constructor initializes the data members to match that /// This constructor initializes the data members to match that
/// of the specified triple. /// of the specified triple.
/// ///
XCoreSubtarget(const std::string &TT, const std::string &CPU, XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM); const std::string &FS, const TargetMachine &TM);
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; } const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const XCoreFrameLowering *getFrameLowering() const override { const XCoreFrameLowering *getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
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llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp

Show All 19 Lines
#define DEBUG_TYPE "xcore-subtarget" #define DEBUG_TYPE "xcore-subtarget"
#define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR #define GET_SUBTARGETINFO_CTOR
#include "XCoreGenSubtargetInfo.inc" #include "XCoreGenSubtargetInfo.inc"
void XCoreSubtarget::anchor() { } void XCoreSubtarget::anchor() { }
XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM) const std::string &FS, const TargetMachine &TM)
: XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
TLInfo(TM, *this), TSInfo(*TM.getDataLayout()) {} TLInfo(TM, *this), TSInfo(*TM.getDataLayout()) {}

llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp

Show All 25 LinesXCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine( : LLVMTargetMachine(
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, RM, CM, OL), TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<XCoreTargetObjectFile>()), TLOF(make_unique<XCoreTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }
XCoreTargetMachine::~XCoreTargetMachine() {} XCoreTargetMachine::~XCoreTargetMachine() {}
namespace { namespace {
/// XCore Code Generator Pass Configuration Options. /// XCore Code Generator Pass Configuration Options.
class XCorePassConfig : public TargetPassConfig { class XCorePassConfig : public TargetPassConfig {
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llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

Show First 20 Lines • Show All 1,431 Lines • ▼ Show 20 Lines#endif
OS << "\n"; OS << "\n";
#if 0 #if 0
OS << "}\n"; OS << "}\n";
#endif #endif
// MCInstrInfo initialization routine. // MCInstrInfo initialization routine.
OS << "static inline void Init" << Target OS << "static inline void Init" << Target
<< "MCSubtargetInfo(MCSubtargetInfo *II, " << "MCSubtargetInfo(MCSubtargetInfo *II, "
<< "StringRef TT, StringRef CPU, StringRef FS) {\n"; << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
if (NumFeatures) if (NumFeatures)
OS << Target << "FeatureKV, "; OS << Target << "FeatureKV, ";
else else
OS << "None, "; OS << "None, ";
if (NumProcs) if (NumProcs)
OS << Target << "SubTypeKV, "; OS << Target << "SubTypeKV, ";
else else
Show All 28 Lines#endif
// Create a TargetSubtargetInfo subclass to hide the MC layer initialization. // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n"; OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
OS << "#undef GET_SUBTARGETINFO_HEADER\n"; OS << "#undef GET_SUBTARGETINFO_HEADER\n";
std::string ClassName = Target + "GenSubtargetInfo"; std::string ClassName = Target + "GenSubtargetInfo";
OS << "namespace llvm {\n"; OS << "namespace llvm {\n";
OS << "class DFAPacketizer;\n"; OS << "class DFAPacketizer;\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
<< " explicit " << ClassName << "(StringRef TT, StringRef CPU, " << " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS);\n" << "StringRef FS);\n"
<< "public:\n" << "public:\n"
<< " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI," << " unsigned resolveSchedClass(unsigned SchedClass, "
<< " const MachineInstr *DefMI,"
<< " const TargetSchedModel *SchedModel) const override;\n" << " const TargetSchedModel *SchedModel) const override;\n"
<< " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
<< " const;\n" << " const;\n"
<< "};\n"; << "};\n";
OS << "} // End llvm namespace \n"; OS << "} // End llvm namespace \n";
OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n"; OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
Show All 13 Lines OS << "extern const llvm::MCReadAdvanceEntry "
<< Target << "ReadAdvanceTable[];\n"; << Target << "ReadAdvanceTable[];\n";
if (SchedModels.hasItineraries()) { if (SchedModels.hasItineraries()) {
OS << "extern const llvm::InstrStage " << Target << "Stages[];\n"; OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
OS << "extern const unsigned " << Target << "OperandCycles[];\n"; OS << "extern const unsigned " << Target << "OperandCycles[];\n";
OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
} }
OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS)\n" << "StringRef FS)\n"
<< " : TargetSubtargetInfo() {\n" << " : TargetSubtargetInfo() {\n"
<< " InitMCSubtargetInfo(TT, CPU, FS, "; << " InitMCSubtargetInfo(TT, CPU, FS, ";
if (NumFeatures) if (NumFeatures)
OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), "; OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
else else
OS << "None, "; OS << "None, ";
if (NumProcs) if (NumProcs)
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