Skip to content

Commit 61105ba

Browse files
dpreobradpreobra
committedJan 18, 2019
[AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions
See bug 39319: https://bugs.llvm.org/show_bug.cgi?id=39319 Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D56847 llvm-svn: 351549
·
llvmorg-21-initllvmorg-9.0.0-rc1
1 parent 47e9a21 commit 61105ba

File tree

6 files changed

+71
-0
lines changed

6 files changed

+71
-0
lines changed
 

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

+39
Original file line numberDiff line numberDiff line change
@@ -1084,6 +1084,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
10841084
OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
10851085

10861086
bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc);
1087+
bool validateSOPLiteral(const MCInst &Inst) const;
10871088
bool validateConstantBusLimitations(const MCInst &Inst);
10881089
bool validateEarlyClobberLimitations(const MCInst &Inst);
10891090
bool validateIntClampSupported(const MCInst &Inst);
@@ -2461,8 +2462,46 @@ bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
24612462
return true;
24622463
}
24632464

2465+
bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
2466+
unsigned Opcode = Inst.getOpcode();
2467+
const MCInstrDesc &Desc = MII.get(Opcode);
2468+
if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC)))
2469+
return true;
2470+
2471+
const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
2472+
const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
2473+
2474+
const int OpIndices[] = { Src0Idx, Src1Idx };
2475+
2476+
unsigned NumLiterals = 0;
2477+
uint32_t LiteralValue;
2478+
2479+
for (int OpIdx : OpIndices) {
2480+
if (OpIdx == -1) break;
2481+
2482+
const MCOperand &MO = Inst.getOperand(OpIdx);
2483+
if (MO.isImm() &&
2484+
// Exclude special imm operands (like that used by s_set_gpr_idx_on)
2485+
AMDGPU::isSISrcOperand(Desc, OpIdx) &&
2486+
!isInlineConstant(Inst, OpIdx)) {
2487+
uint32_t Value = static_cast<uint32_t>(MO.getImm());
2488+
if (NumLiterals == 0 || LiteralValue != Value) {
2489+
LiteralValue = Value;
2490+
++NumLiterals;
2491+
}
2492+
}
2493+
}
2494+
2495+
return NumLiterals <= 1;
2496+
}
2497+
24642498
bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
24652499
const SMLoc &IDLoc) {
2500+
if (!validateSOPLiteral(Inst)) {
2501+
Error(IDLoc,
2502+
"only one literal operand is allowed");
2503+
return false;
2504+
}
24662505
if (!validateConstantBusLimitations(Inst)) {
24672506
Error(IDLoc,
24682507
"invalid operand (violates constant bus restrictions)");

‎llvm/lib/Target/AMDGPU/SOPInstructions.td

+2
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,8 @@ class SOP2_Real<bits<7> op, SOP_Pseudo ps> :
302302
// copy relevant pseudo op flags
303303
let SubtargetPredicate = ps.SubtargetPredicate;
304304
let AsmMatchConverter = ps.AsmMatchConverter;
305+
let UseNamedOperandTable = ps.UseNamedOperandTable;
306+
let TSFlags = ps.TSFlags;
305307

306308
// encoding
307309
bits<7> sdst;

‎llvm/test/MC/AMDGPU/sop2-err.s

+6
Original file line numberDiff line numberDiff line change
@@ -5,3 +5,9 @@ s_cbranch_g_fork 100, s[6:7]
55

66
s_cbranch_g_fork s[6:7], 100
77
// GCN: error: invalid operand for instruction
8+
9+
s_and_b32 s2, 0x12345678, 0x12345679
10+
// GCN: error: only one literal operand is allowed
11+
12+
s_and_b64 s[2:3], 0x12345678, 0x12345679
13+
// GCN: error: only one literal operand is allowed

‎llvm/test/MC/AMDGPU/sop2.s

+12
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,14 @@ s_and_b32 s2, s4, s6
5050
// SICI: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87]
5151
// GFX89: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x86]
5252

53+
s_and_b32 s2, 1234, 1234
54+
// SICI: s_and_b32 s2, 0x4d2, 0x4d2 ; encoding: [0xff,0xff,0x02,0x87,0xd2,0x04,0x00,0x00]
55+
// GFX89: s_and_b32 s2, 0x4d2, 0x4d2 ; encoding: [0xff,0xff,0x02,0x86,0xd2,0x04,0x00,0x00]
56+
57+
s_and_b32 s2, 0xFFFF0000, -65536
58+
// SICI: s_and_b32 s2, 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x02,0x87,0x00,0x00,0xff,0xff]
59+
// GFX89: s_and_b32 s2, 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x02,0x86,0x00,0x00,0xff,0xff]
60+
5361
s_and_b64 s[2:3], s[4:5], s[6:7]
5462
// SICI: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
5563
// GFX89: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x86]
@@ -134,6 +142,10 @@ s_ashr_i64 s[2:3], s[4:5], s6
134142
// SICI: s_ashr_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x91]
135143
// GFX89: s_ashr_i64 s[2:3], s[4:5], s6 ; encoding: [0x04,0x06,0x82,0x90]
136144

145+
s_ashr_i64 s[2:3], -65536, 0xFFFF0000
146+
// SICI: s_ashr_i64 s[2:3], 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x82,0x91,0x00,0x00,0xff,0xff]
147+
// GFX89: s_ashr_i64 s[2:3], 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x82,0x90,0x00,0x00,0xff,0xff]
148+
137149
s_bfm_b32 s2, s4, s6
138150
// SICI: s_bfm_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x92]
139151
// GFX89: s_bfm_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x91]

‎llvm/test/MC/AMDGPU/sopc-err.s

+6
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,9 @@ s_set_gpr_idx_on s0, 16
88

99
s_set_gpr_idx_on s0, -1
1010
// GCN: error: invalid operand for instruction
11+
12+
s_cmp_eq_i32 0x12345678, 0x12345679
13+
// GCN: error: only one literal operand is allowed
14+
15+
s_cmp_eq_u64 0x12345678, 0x12345679
16+
// GCN: error: only one literal operand is allowed

‎llvm/test/MC/AMDGPU/sopc.s

+6
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,12 @@
99
s_cmp_eq_i32 s1, s2
1010
// GCN: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
1111

12+
s_cmp_eq_i32 0xabcd1234, 0xabcd1234
13+
// GCN: s_cmp_eq_i32 0xabcd1234, 0xabcd1234 ; encoding: [0xff,0xff,0x00,0xbf,0x34,0x12,0xcd,0xab]
14+
15+
s_cmp_eq_i32 0xFFFF0000, -65536
16+
// GCN: s_cmp_eq_i32 0xffff0000, 0xffff0000 ; encoding: [0xff,0xff,0x00,0xbf,0x00,0x00,0xff,0xff]
17+
1218
s_cmp_lg_i32 s1, s2
1319
// GCN: s_cmp_lg_i32 s1, s2 ; encoding: [0x01,0x02,0x01,0xbf]
1420

0 commit comments

Comments
 (0)
Please sign in to comment.