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Differential D53861

[mips] Support sigrie instruction
ClosedPublic

Authored by atanasyan on Oct 29 2018, 10:41 PM.

Details

Reviewers
abeserminji
petarj
smaksimovic
Commits
rGbb36aea1d5c9: [mips] Support sigrie instruction
rL346230: [mips] Support sigrie instruction
Summary

The sigrie instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction.

Diff Detail

Repository
rL LLVM

Event Timeline

atanasyan created this revision.Oct 29 2018, 10:41 PM
Herald added subscribers: jrtc27, arichardson, sdardis. · View Herald TranscriptOct 29 2018, 10:41 PM
smaksimovic accepted this revision.Nov 2 2018, 1:11 AM

LGTM

This revision is now accepted and ready to land.Nov 2 2018, 1:11 AM
Closed by commit rL346230: [mips] Support sigrie instruction (authored by atanasyan). · Explain WhyNov 6 2018, 6:41 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
11 lines
11 lines
10 lines
12 lines
2 lines
2 lines
test/
MC/
Mips/
micromips32r6/
4 lines
mips32r6/
4 lines
mips64r6/
4 lines

Diff 172758

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

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class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>; class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6; class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">; class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">; class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6; class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">; class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>; class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">; class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>; class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>; class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>; class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>; class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>; class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>; class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>; class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>; class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
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class SDBBP_MMR6_DESC : MipsR6Inst { class SDBBP_MMR6_DESC : MipsR6Inst {
dag OutOperandList = (outs); dag OutOperandList = (outs);
dag InOperandList = (ins uimm20:$code_); dag InOperandList = (ins uimm20:$code_);
string AsmString = !strconcat("sdbbp", "\t$code_"); string AsmString = !strconcat("sdbbp", "\t$code_");
list<dag> Pattern = []; list<dag> Pattern = [];
InstrItinClass Itinerary = II_SDBBP; InstrItinClass Itinerary = II_SDBBP;
} }
class SIGRIE_MMR6_DESC : MipsR6Inst {
dag OutOperandList = (outs);
dag InOperandList = (ins uimm16:$code_);
string AsmString = !strconcat("sigrie", "\t$code_");
list<dag> Pattern = [];
InstrItinClass Itinerary = II_SIGRIE;
}
class LWM16_MMR6_DESC class LWM16_MMR6_DESC
: MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr), : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
!strconcat("lwm16", "\t$rt, $addr"), [], !strconcat("lwm16", "\t$rt, $addr"), [],
II_LWM, FrmI>, II_LWM, FrmI>,
MMR6Arch<"lwm16"> { MMR6Arch<"lwm16"> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayLoad = 1; let mayLoad = 1;
ComplexPattern Addr = addr; ComplexPattern Addr = addr;
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def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6; def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6; def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6; def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6; def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6; def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC, def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6; def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6; def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6; def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6; def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
} }
/// Floating Point Instructions /// Floating Point Instructions
def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC, def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
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def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6; def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6; def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset), def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
!strconcat("b", "\t$offset")> { !strconcat("b", "\t$offset")> {
string DecoderNamespace = "MicroMipsR6"; string DecoderNamespace = "MicroMipsR6";
} }
def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6; def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6; def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
def : MipsInstAlias<"rdhwr $rt, $rs", def : MipsInstAlias<"rdhwr $rt, $rs",
(RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"mtc0 $rt, $rs", def : MipsInstAlias<"mtc0 $rt, $rs",
(MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def : MipsInstAlias<"mthc0 $rt, $rs", def : MipsInstAlias<"mthc0 $rt, $rs",
(MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>, (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
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llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 927 Lines • ▼ Show 20 Linesclass SDBBP_FM_MM : MMArch {
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x0; let Inst{31-26} = 0x0;
let Inst{25-16} = code_; let Inst{25-16} = code_;
let Inst{15-6} = 0x36d; let Inst{15-6} = 0x36d;
let Inst{5-0} = 0x3c; let Inst{5-0} = 0x3c;
} }
class SIGRIE_FM_MM : MMArch {
bits<16> code_;
bits<32> Inst;
let Inst{31-26} = 0x0;
let Inst{25-22} = 0x0;
let Inst{21-6} = code_;
let Inst{5-0} = 0b111111;
}
class RDHWR_FM_MM : MMArch { class RDHWR_FM_MM : MMArch {
bits<5> rt; bits<5> rt;
bits<5> rd; bits<5> rd;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x0; let Inst{31-26} = 0x0;
let Inst{25-21} = rt; let Inst{25-21} = rt;
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llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td

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def OPCODE5_AUIPC : OPCODE5<0b11110>; def OPCODE5_AUIPC : OPCODE5<0b11110>;
def OPCODE5_DAHI : OPCODE5<0b00110>; def OPCODE5_DAHI : OPCODE5<0b00110>;
def OPCODE5_DATI : OPCODE5<0b11110>; def OPCODE5_DATI : OPCODE5<0b11110>;
def OPCODE5_BC1EQZ : OPCODE5<0b01001>; def OPCODE5_BC1EQZ : OPCODE5<0b01001>;
def OPCODE5_BC1NEZ : OPCODE5<0b01101>; def OPCODE5_BC1NEZ : OPCODE5<0b01101>;
def OPCODE5_BC2EQZ : OPCODE5<0b01001>; def OPCODE5_BC2EQZ : OPCODE5<0b01001>;
def OPCODE5_BC2NEZ : OPCODE5<0b01101>; def OPCODE5_BC2NEZ : OPCODE5<0b01101>;
def OPCODE5_BGEZAL : OPCODE5<0b10001>; def OPCODE5_BGEZAL : OPCODE5<0b10001>;
def OPCODE5_SIGRIE : OPCODE5<0b10111>;
// The next four constants are unnamed in the spec. These names are taken from // The next four constants are unnamed in the spec. These names are taken from
// the OPGROUP names they are used with. // the OPGROUP names they are used with.
def OPCODE5_LDC2 : OPCODE5<0b01110>; def OPCODE5_LDC2 : OPCODE5<0b01110>;
def OPCODE5_LWC2 : OPCODE5<0b01010>; def OPCODE5_LWC2 : OPCODE5<0b01010>;
def OPCODE5_SDC2 : OPCODE5<0b01111>; def OPCODE5_SDC2 : OPCODE5<0b01111>;
def OPCODE5_SWC2 : OPCODE5<0b01011>; def OPCODE5_SWC2 : OPCODE5<0b01011>;
class OPCODE6<bits<6> Val> { class OPCODE6<bits<6> Val> {
▲ Show 20 Lines • Show All 499 Lines • ▼ Show 20 Linesclass SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
let Inst{31-26} = OPGROUP_SPECIAL3.Value; let Inst{31-26} = OPGROUP_SPECIAL3.Value;
let Inst{25-21} = rs; let Inst{25-21} = rs;
let Inst{20-10} = 0x0; let Inst{20-10} = 0x0;
let Inst{9-8} = type_; let Inst{9-8} = type_;
let Inst{7-6} = ginv; let Inst{7-6} = ginv;
let Inst{5-0} = 0b111101; let Inst{5-0} = 0b111101;
} }
class SIGRIE_FM : MipsR6Inst {
bits<16> code_;
let Inst{31-26} = OPGROUP_REGIMM.Value;
let Inst{25-21} = 0;
let Inst{20-16} = OPCODE5_SIGRIE.Value;
let Inst{15-0} = code_;
}

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

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class CRC32W_ENC : SPECIAL3_2R_SZ_CRC<2,0>; class CRC32W_ENC : SPECIAL3_2R_SZ_CRC<2,0>;
class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>; class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;
class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>; class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;
class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>; class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
class GINVI_ENC : SPECIAL3_GINV<0>; class GINVI_ENC : SPECIAL3_GINV<0>;
class GINVT_ENC : SPECIAL3_GINV<2>; class GINVT_ENC : SPECIAL3_GINV<2>;
class SIGRIE_ENC : SIGRIE_FM;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Multiclasses // Instruction Multiclasses
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
RegisterOperand FGROpnd, RegisterOperand FGROpnd,
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} }
class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> { class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
dag InOperandList = (ins GPR32Opnd:$rs); dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = "ginvi\t$rs"; string AsmString = "ginvi\t$rs";
} }
class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>; class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
class SIGRIE_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins uimm16:$code_);
string AsmString = "sigrie\t$code_";
list<dag> Pattern = [];
InstrItinClass Itinerary = II_SIGRIE;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, def SELNEZ_D : R6MMR6Rel, SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6,
HARDFLOAT; HARDFLOAT;
def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
HARDFLOAT; HARDFLOAT;
def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT; def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT; def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6; def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
def SIGRIE : SIGRIE_ENC, SIGRIE_DESC, ISA_MIPS32R6;
} }
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC; def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC;
def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC; def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC;
def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC; def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC;
def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC; def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC;
def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC; def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC;
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// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6; def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6; def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"sigrie", (SIGRIE 0)>, ISA_MIPS32R6;
def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32; def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
} }
def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32; def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
} }
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llvm/trunk/lib/Target/Mips/MipsSchedule.td

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def II_JRADDIUSP : InstrItinClass; def II_JRADDIUSP : InstrItinClass;
def II_JRC : InstrItinClass; def II_JRC : InstrItinClass;
def II_ReturnPseudo : InstrItinClass; // Return pseudo. def II_ReturnPseudo : InstrItinClass; // Return pseudo.
def II_ERET : InstrItinClass; def II_ERET : InstrItinClass;
def II_DERET : InstrItinClass; def II_DERET : InstrItinClass;
def II_ERETNC : InstrItinClass; def II_ERETNC : InstrItinClass;
def II_EHB : InstrItinClass; def II_EHB : InstrItinClass;
def II_SDBBP : InstrItinClass; def II_SDBBP : InstrItinClass;
def II_SIGRIE : InstrItinClass;
def II_SSNOP : InstrItinClass; def II_SSNOP : InstrItinClass;
def II_SYSCALL : InstrItinClass; def II_SYSCALL : InstrItinClass;
def II_PAUSE : InstrItinClass; def II_PAUSE : InstrItinClass;
def II_WAIT : InstrItinClass; def II_WAIT : InstrItinClass;
def II_EI : InstrItinClass; def II_EI : InstrItinClass;
def II_DI : InstrItinClass; def II_DI : InstrItinClass;
def II_TEQ : InstrItinClass; def II_TEQ : InstrItinClass;
def II_TEQI : InstrItinClass; def II_TEQI : InstrItinClass;
▲ Show 20 Lines • Show All 376 Lines • ▼ Show 20 Linesdef MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIPseudo , [InstrStage<1, [ALU]>]>, InstrItinData<IIPseudo , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>,
InstrItinData<II_ERET , [InstrStage<1, [ALU]>]>, InstrItinData<II_ERET , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DERET , [InstrStage<1, [ALU]>]>, InstrItinData<II_DERET , [InstrStage<1, [ALU]>]>,
InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>, InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>,
InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>, InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>, InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SIGRIE , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>, InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>,
InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>, InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>,
InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>, InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
InstrItinData<II_WAIT , [InstrStage<1, [ALU]>]>, InstrItinData<II_WAIT , [InstrStage<1, [ALU]>]>,
InstrItinData<II_EI , [InstrStage<1, [ALU]>]>, InstrItinData<II_EI , [InstrStage<1, [ALU]>]>,
InstrItinData<II_DI , [InstrStage<1, [ALU]>]>, InstrItinData<II_DI , [InstrStage<1, [ALU]>]>,
InstrItinData<II_TEQ , [InstrStage<1, [ALU]>]>, InstrItinData<II_TEQ , [InstrStage<1, [ALU]>]>,
InstrItinData<II_TEQI , [InstrStage<1, [ALU]>]>, InstrItinData<II_TEQI , [InstrStage<1, [ALU]>]>,
▲ Show 20 Lines • Show All 180 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td

Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Lines
def : ItinRW<[GenericWriteJump], [II_JIC, II_BC, II_BCCC, II_BCCZC]>; def : ItinRW<[GenericWriteJump], [II_JIC, II_BC, II_BCCC, II_BCCZC]>;
def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>; def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>;
def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI, def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI,
II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE, II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE,
II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU, II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU,
II_TRAP, II_SDBBP]>; II_TRAP, II_SDBBP, II_SIGRIE]>;
// COP0 Pipeline // COP0 Pipeline
// ============= // =============
def GenericCOP0 : ProcResource<1> { let BufferSize = 1; } def GenericCOP0 : ProcResource<1> { let BufferSize = 1; }
def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; } def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; }
def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; } def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; }
▲ Show 20 Lines • Show All 876 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
wait 17 # CHECK: wait 17 # encoding: [0x00,0x11,0x93,0x7c] wait 17 # CHECK: wait 17 # encoding: [0x00,0x11,0x93,0x7c]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00]
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c] sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
sync 17 # CHECK: sync 17 # encoding: [0x00,0x11,0x6b,0x7c] sync 17 # CHECK: sync 17 # encoding: [0x00,0x11,0x6b,0x7c]
synci 8($5) # CHECK: synci 8($5) # encoding: [0x41,0x85,0x00,0x08] synci 8($5) # CHECK: synci 8($5) # encoding: [0x41,0x85,0x00,0x08]
rdpgpr $3, $9 # CHECK: $3, $9 # encoding: [0x00,0x69,0xe1,0x7c] rdpgpr $3, $9 # CHECK: $3, $9 # encoding: [0x00,0x69,0xe1,0x7c]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c] sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
sigrie # CHECK: sigrie # encoding: [0x00,0x00,0x00,0x3f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE_MM
sigrie 257 # CHECK: sigrie 257 # encoding: [0x00,0x00,0x40,0x7f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE_MM
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30] add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30] add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM # CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM
sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70] sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70] sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
▲ Show 20 Lines • Show All 253 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Linesa:
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e] sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sigrie # CHECK: sigrie # encoding: [0x04,0x17,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sigrie 257 # CHECK: sigrie 257 # encoding: [0x04,0x17,0x01,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC # CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC # CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Linesa:
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e] sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sigrie # CHECK: sigrie # encoding: [0x04,0x17,0x00,0x00]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sigrie 257 # CHECK: sigrie 257 # encoding: [0x04,0x17,0x01,0x01]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SIGRIE
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35]
seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14]
seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14]
selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37]
selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17]
▲ Show 20 Lines • Show All 117 Lines • Show Last 20 Lines