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tlivelytlively
committedOct 24, 2018
[NFC] Rename minnan and maxnan to minimum and maximum
Summary: Changes all uses of minnan/maxnan to minimum/maximum globally. These names emphasize that the semantic difference between these operations is more than just NaN-propagation. Reviewers: arsenm, aheejin, dschuff, javed.absar Subscribers: jholewinski, sdardis, wdng, sbc100, jgravelle-google, jrtc27, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D53112 llvm-svn: 345218
1 parent 654d3a9 commit 30f1d69

27 files changed

+124
-127
lines changed
 

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -1073,12 +1073,12 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
10731073
case Intrinsic::minnum:
10741074
ISDs.push_back(ISD::FMINNUM);
10751075
if (FMF.noNaNs())
1076-
ISDs.push_back(ISD::FMINNAN);
1076+
ISDs.push_back(ISD::FMINIMUM);
10771077
break;
10781078
case Intrinsic::maxnum:
10791079
ISDs.push_back(ISD::FMAXNUM);
10801080
if (FMF.noNaNs())
1081-
ISDs.push_back(ISD::FMAXNAN);
1081+
ISDs.push_back(ISD::FMAXIMUM);
10821082
break;
10831083
case Intrinsic::copysign:
10841084
ISDs.push_back(ISD::FCOPYSIGN);

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

+4-4
Original file line numberDiff line numberDiff line change
@@ -577,10 +577,10 @@ namespace ISD {
577577
/// signaling NaN, returns a quiet NaN.
578578
FMINNUM_IEEE, FMAXNUM_IEEE,
579579

580-
/// FMINNAN/FMAXNAN - NaN-propagating minimum/maximum that also treat -0.0
581-
/// as less than 0.0. While FMINNUM/FMAXNUM follow IEEE 754-2008 semantics,
582-
/// FMINNAN/FMAXNAN follow IEEE 754-2018 draft semantics.
583-
FMINNAN, FMAXNAN,
580+
/// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
581+
/// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
582+
/// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
583+
FMINIMUM, FMAXIMUM,
584584

585585
/// FSINCOS - Compute both fsin and fcos as a single operation.
586586
FSINCOS,

‎llvm/include/llvm/CodeGen/TargetLowering.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -2099,8 +2099,8 @@ class TargetLoweringBase {
20992099
case ISD::ADDE:
21002100
case ISD::FMINNUM:
21012101
case ISD::FMAXNUM:
2102-
case ISD::FMINNAN:
2103-
case ISD::FMAXNAN:
2102+
case ISD::FMINIMUM:
2103+
case ISD::FMAXIMUM:
21042104
return true;
21052105
default: return false;
21062106
}

‎llvm/include/llvm/Target/TargetSelectionDAG.td

+2-3
Original file line numberDiff line numberDiff line change
@@ -413,9 +413,8 @@ def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp,
413413
[SDNPCommutative]>;
414414
def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
415415
[SDNPCommutative]>;
416-
417-
def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
418-
def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
416+
def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp>;
417+
def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp>;
419418
def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
420419
def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;
421420
def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -371,8 +371,8 @@ namespace {
371371
SDValue visitFFLOOR(SDNode *N);
372372
SDValue visitFMINNUM(SDNode *N);
373373
SDValue visitFMAXNUM(SDNode *N);
374-
SDValue visitFMINNAN(SDNode *N);
375-
SDValue visitFMAXNAN(SDNode *N);
374+
SDValue visitFMINIMUM(SDNode *N);
375+
SDValue visitFMAXIMUM(SDNode *N);
376376
SDValue visitBRCOND(SDNode *N);
377377
SDValue visitBR_CC(SDNode *N);
378378
SDValue visitLOAD(SDNode *N);
@@ -1584,8 +1584,8 @@ SDValue DAGCombiner::visit(SDNode *N) {
15841584
case ISD::FFLOOR: return visitFFLOOR(N);
15851585
case ISD::FMINNUM: return visitFMINNUM(N);
15861586
case ISD::FMAXNUM: return visitFMAXNUM(N);
1587-
case ISD::FMINNAN: return visitFMINNAN(N);
1588-
case ISD::FMAXNAN: return visitFMAXNAN(N);
1587+
case ISD::FMINIMUM: return visitFMINIMUM(N);
1588+
case ISD::FMAXIMUM: return visitFMAXIMUM(N);
15891589
case ISD::FCEIL: return visitFCEIL(N);
15901590
case ISD::FTRUNC: return visitFTRUNC(N);
15911591
case ISD::BRCOND: return visitBRCOND(N);
@@ -12158,11 +12158,11 @@ SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
1215812158
return visitFMinMax(DAG, N, maxnum);
1215912159
}
1216012160

12161-
SDValue DAGCombiner::visitFMINNAN(SDNode *N) {
12161+
SDValue DAGCombiner::visitFMINIMUM(SDNode *N) {
1216212162
return visitFMinMax(DAG, N, minimum);
1216312163
}
1216412164

12165-
SDValue DAGCombiner::visitFMAXNAN(SDNode *N) {
12165+
SDValue DAGCombiner::visitFMAXIMUM(SDNode *N) {
1216612166
return visitFMinMax(DAG, N, maximum);
1216712167
}
1216812168

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1910,8 +1910,8 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
19101910
// Binary FP Operations
19111911
case ISD::FADD:
19121912
case ISD::FDIV:
1913-
case ISD::FMAXNAN:
1914-
case ISD::FMINNAN:
1913+
case ISD::FMAXIMUM:
1914+
case ISD::FMINIMUM:
19151915
case ISD::FMAXNUM:
19161916
case ISD::FMINNUM:
19171917
case ISD::FMUL:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -356,8 +356,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
356356
case ISD::FMAXNUM:
357357
case ISD::FMINNUM_IEEE:
358358
case ISD::FMAXNUM_IEEE:
359-
case ISD::FMINNAN:
360-
case ISD::FMAXNAN:
359+
case ISD::FMINIMUM:
360+
case ISD::FMAXIMUM:
361361
case ISD::FCOPYSIGN:
362362
case ISD::FSQRT:
363363
case ISD::FSIN:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

+8-8
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
115115
case ISD::FMAXNUM:
116116
case ISD::FMINNUM_IEEE:
117117
case ISD::FMAXNUM_IEEE:
118-
case ISD::FMINNAN:
119-
case ISD::FMAXNAN:
118+
case ISD::FMINIMUM:
119+
case ISD::FMAXIMUM:
120120
case ISD::SMIN:
121121
case ISD::SMAX:
122122
case ISD::UMIN:
@@ -786,8 +786,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
786786
case ISD::FMUL:
787787
case ISD::FMINNUM:
788788
case ISD::FMAXNUM:
789-
case ISD::FMINNAN:
790-
case ISD::FMAXNAN:
789+
case ISD::FMINIMUM:
790+
case ISD::FMAXIMUM:
791791
case ISD::SDIV:
792792
case ISD::UDIV:
793793
case ISD::FDIV:
@@ -1804,10 +1804,10 @@ SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
18041804
case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
18051805
case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
18061806
case ISD::VECREDUCE_FMAX:
1807-
CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN;
1807+
CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
18081808
break;
18091809
case ISD::VECREDUCE_FMIN:
1810-
CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN;
1810+
CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
18111811
break;
18121812
default:
18131813
llvm_unreachable("Unexpected reduce ISD node");
@@ -2356,8 +2356,8 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
23562356
case ISD::XOR:
23572357
case ISD::FMINNUM:
23582358
case ISD::FMAXNUM:
2359-
case ISD::FMINNAN:
2360-
case ISD::FMAXNAN:
2359+
case ISD::FMINIMUM:
2360+
case ISD::FMAXIMUM:
23612361
case ISD::SMIN:
23622362
case ISD::SMAX:
23632363
case ISD::UMIN:

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -3730,12 +3730,11 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
37303730
(isKnownNeverNaN(Op.getOperand(1), false, Depth + 1) &&
37313731
isKnownNeverSNaN(Op.getOperand(0), Depth + 1));
37323732
}
3733-
case ISD::FMINNAN:
3734-
case ISD::FMAXNAN: {
3733+
case ISD::FMINIMUM:
3734+
case ISD::FMAXIMUM: {
37353735
// TODO: Does this quiet or return the origina NaN as-is?
37363736
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
37373737
isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
3738-
37393738
}
37403739
case ISD::EXTRACT_VECTOR_ELT: {
37413740
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+14-14
Original file line numberDiff line numberDiff line change
@@ -2972,34 +2972,34 @@ void SelectionDAGBuilder::visitSelect(const User &I) {
29722972
case SPF_FMINNUM:
29732973
switch (SPR.NaNBehavior) {
29742974
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2975-
case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2975+
case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
29762976
case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
29772977
case SPNB_RETURNS_ANY: {
29782978
if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
29792979
Opc = ISD::FMINNUM;
2980-
else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2981-
Opc = ISD::FMINNAN;
2980+
else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
2981+
Opc = ISD::FMINIMUM;
29822982
else if (UseScalarMinMax)
29832983
Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
2984-
ISD::FMINNUM : ISD::FMINNAN;
2984+
ISD::FMINNUM : ISD::FMINIMUM;
29852985
break;
29862986
}
29872987
}
29882988
break;
29892989
case SPF_FMAXNUM:
29902990
switch (SPR.NaNBehavior) {
29912991
case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2992-
case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2992+
case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break;
29932993
case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
29942994
case SPNB_RETURNS_ANY:
29952995

29962996
if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
29972997
Opc = ISD::FMAXNUM;
2998-
else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT))
2999-
Opc = ISD::FMAXNAN;
2998+
else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT))
2999+
Opc = ISD::FMAXIMUM;
30003000
else if (UseScalarMinMax)
30013001
Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
3002-
ISD::FMAXNUM : ISD::FMAXNAN;
3002+
ISD::FMAXNUM : ISD::FMAXIMUM;
30033003
break;
30043004
}
30053005
break;
@@ -5565,8 +5565,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
55655565
case Intrinsic::minnum: {
55665566
auto VT = getValue(I.getArgOperand(0)).getValueType();
55675567
unsigned Opc =
5568-
I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)
5569-
? ISD::FMINNAN
5568+
I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT)
5569+
? ISD::FMINIMUM
55705570
: ISD::FMINNUM;
55715571
setValue(&I, DAG.getNode(Opc, sdl, VT,
55725572
getValue(I.getArgOperand(0)),
@@ -5576,22 +5576,22 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
55765576
case Intrinsic::maxnum: {
55775577
auto VT = getValue(I.getArgOperand(0)).getValueType();
55785578
unsigned Opc =
5579-
I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)
5580-
? ISD::FMAXNAN
5579+
I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)
5580+
? ISD::FMAXIMUM
55815581
: ISD::FMAXNUM;
55825582
setValue(&I, DAG.getNode(Opc, sdl, VT,
55835583
getValue(I.getArgOperand(0)),
55845584
getValue(I.getArgOperand(1))));
55855585
return nullptr;
55865586
}
55875587
case Intrinsic::minimum:
5588-
setValue(&I, DAG.getNode(ISD::FMINNAN, sdl,
5588+
setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl,
55895589
getValue(I.getArgOperand(0)).getValueType(),
55905590
getValue(I.getArgOperand(0)),
55915591
getValue(I.getArgOperand(1))));
55925592
return nullptr;
55935593
case Intrinsic::maximum:
5594-
setValue(&I, DAG.getNode(ISD::FMAXNAN, sdl,
5594+
setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl,
55955595
getValue(I.getArgOperand(0)).getValueType(),
55965596
getValue(I.getArgOperand(0)),
55975597
getValue(I.getArgOperand(1))));

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -178,9 +178,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
178178
case ISD::FMAXNUM: return "fmaxnum";
179179
case ISD::FMINNUM_IEEE: return "fminnum_ieee";
180180
case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee";
181-
182-
case ISD::FMINNAN: return "fminnan";
183-
case ISD::FMAXNAN: return "fmaxnan";
181+
case ISD::FMINIMUM: return "fminimum";
182+
case ISD::FMAXIMUM: return "fmaximum";
184183
case ISD::FNEG: return "fneg";
185184
case ISD::FSQRT: return "fsqrt";
186185
case ISD::STRICT_FSQRT: return "strict_fsqrt";

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -602,8 +602,8 @@ void TargetLoweringBase::initActions() {
602602
setOperationAction(ISD::FMAXNUM, VT, Expand);
603603
setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
604604
setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand);
605-
setOperationAction(ISD::FMINNAN, VT, Expand);
606-
setOperationAction(ISD::FMAXNAN, VT, Expand);
605+
setOperationAction(ISD::FMINIMUM, VT, Expand);
606+
setOperationAction(ISD::FMAXIMUM, VT, Expand);
607607
setOperationAction(ISD::FMAD, VT, Expand);
608608
setOperationAction(ISD::SMIN, VT, Expand);
609609
setOperationAction(ISD::SMAX, VT, Expand);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+10-10
Original file line numberDiff line numberDiff line change
@@ -385,8 +385,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
385385
setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
386386
setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
387387
setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
388-
setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
389-
setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
388+
setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
389+
setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
390390

391391
// promote v4f16 to v4f32 when that is known to be safe.
392392
setOperationAction(ISD::FADD, MVT::v4f16, Promote);
@@ -450,8 +450,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
450450
setOperationAction(ISD::FROUND, Ty, Legal);
451451
setOperationAction(ISD::FMINNUM, Ty, Legal);
452452
setOperationAction(ISD::FMAXNUM, Ty, Legal);
453-
setOperationAction(ISD::FMINNAN, Ty, Legal);
454-
setOperationAction(ISD::FMAXNAN, Ty, Legal);
453+
setOperationAction(ISD::FMINIMUM, Ty, Legal);
454+
setOperationAction(ISD::FMAXIMUM, Ty, Legal);
455455
}
456456

457457
if (Subtarget->hasFullFP16()) {
@@ -463,8 +463,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
463463
setOperationAction(ISD::FROUND, MVT::f16, Legal);
464464
setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
465465
setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
466-
setOperationAction(ISD::FMINNAN, MVT::f16, Legal);
467-
setOperationAction(ISD::FMAXNAN, MVT::f16, Legal);
466+
setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
467+
setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
468468
}
469469

470470
setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
@@ -816,8 +816,8 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
816816
// F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
817817
if (VT.isFloatingPoint() &&
818818
(VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
819-
for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
820-
ISD::FMINNUM, ISD::FMAXNUM})
819+
for (unsigned Opcode :
820+
{ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
821821
setOperationAction(Opcode, VT, Legal);
822822

823823
if (Subtarget->isLittleEndian()) {
@@ -9867,10 +9867,10 @@ static SDValue performIntrinsicCombine(SDNode *N,
98679867
case Intrinsic::aarch64_neon_umaxv:
98689868
return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG);
98699869
case Intrinsic::aarch64_neon_fmax:
9870-
return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0),
9870+
return DAG.getNode(ISD::FMAXIMUM, SDLoc(N), N->getValueType(0),
98719871
N->getOperand(1), N->getOperand(2));
98729872
case Intrinsic::aarch64_neon_fmin:
9873-
return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0),
9873+
return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0),
98749874
N->getOperand(1), N->getOperand(2));
98759875
case Intrinsic::aarch64_neon_fmaxnm:
98769876
return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0),

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

+6-6
Original file line numberDiff line numberDiff line change
@@ -3050,18 +3050,18 @@ let SchedRW = [WriteFDiv] in {
30503050
defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
30513051
}
30523052
defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
3053-
defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
3053+
defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaximum>;
30543054
defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
3055-
defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
3055+
defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>;
30563056
let SchedRW = [WriteFMul] in {
30573057
defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
30583058
defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
30593059
}
30603060
defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
30613061

3062-
def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3062+
def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
30633063
(FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
3064-
def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3064+
def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(FMINDrr FPR64:$Rn, FPR64:$Rm)>;
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def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
@@ -3387,11 +3387,11 @@ defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>;
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defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
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defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>;
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defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>;
3390-
defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>;
3390+
defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaximum>;
33913391
defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>;
33923392
defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>;
33933393
defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;
3394-
defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>;
3394+
defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>;
33953395

33963396
// NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
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// instruction expects the addend first, while the fma intrinsic puts it last.

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