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author
Simon Dardis
committedFeb 13, 2017
[mips] divide macro instruction cleanup.
Clean up the implementation of divide macro expansion by getting rid of a FIXME regarding magic numbers and branch instructions. Match GAS' behaviour for expansion of ddiv / div in the two and three operand cases. Add the two operand alias for MIPSR6. Finally, optimize macro expansion cases where the divisior is the $zero register. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29887 llvm-svn: 294960
·
llvmorg-21-initllvmorg-5.0.0-rc1
1 parent fd6a84f commit 509da1a

11 files changed

+353
-193
lines changed
 

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

+117-46
Original file line numberDiff line numberDiff line change
@@ -968,6 +968,16 @@ class MipsOperand : public MCParsedAsmOperand {
968968
/// Render the operand to an MCInst as a GPR32
969969
/// Asserts if the wrong number of operands are requested, or the operand
970970
/// is not a k_RegisterIndex compatible with RegKind_GPR
971+
void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
972+
assert(N == 1 && "Invalid number of operands!");
973+
Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
974+
}
975+
976+
void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
977+
assert(N == 1 && "Invalid number of operands!");
978+
Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
979+
}
980+
971981
void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
972982
assert(N == 1 && "Invalid number of operands!");
973983
Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
@@ -1524,6 +1534,15 @@ class MipsOperand : public MCParsedAsmOperand {
15241534
return Op;
15251535
}
15261536

1537+
bool isGPRZeroAsmReg() const {
1538+
return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index == 0;
1539+
}
1540+
1541+
bool isGPRNonZeroAsmReg() const {
1542+
return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index > 0 &&
1543+
RegIdx.Index <= 31;
1544+
}
1545+
15271546
bool isGPRAsmReg() const {
15281547
return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
15291548
}
@@ -1883,6 +1902,61 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
18831902
}
18841903
}
18851904

1905+
// Warn on division by zero. We're checking here as all instructions get
1906+
// processed here, not just the macros that need expansion.
1907+
//
1908+
// The MIPS backend models most of the divison instructions and macros as
1909+
// three operand instructions. The pre-R6 divide instructions however have
1910+
// two operands and explicitly define HI/LO as part of the instruction,
1911+
// not in the operands.
1912+
unsigned FirstOp = 1;
1913+
unsigned SecondOp = 2;
1914+
switch (Inst.getOpcode()) {
1915+
default:
1916+
break;
1917+
case Mips::SDivIMacro:
1918+
case Mips::UDivIMacro:
1919+
case Mips::DSDivIMacro:
1920+
case Mips::DUDivIMacro:
1921+
if (Inst.getOperand(2).getImm() == 0) {
1922+
if (Inst.getOperand(1).getReg() == Mips::ZERO ||
1923+
Inst.getOperand(1).getReg() == Mips::ZERO_64)
1924+
Warning(IDLoc, "dividing zero by zero");
1925+
else
1926+
Warning(IDLoc, "division by zero");
1927+
}
1928+
break;
1929+
case Mips::DSDIV:
1930+
case Mips::SDIV:
1931+
case Mips::UDIV:
1932+
case Mips::DUDIV:
1933+
case Mips::UDIV_MM:
1934+
case Mips::SDIV_MM:
1935+
FirstOp = 0;
1936+
SecondOp = 1;
1937+
case Mips::SDivMacro:
1938+
case Mips::DSDivMacro:
1939+
case Mips::UDivMacro:
1940+
case Mips::DUDivMacro:
1941+
case Mips::DIV:
1942+
case Mips::DIVU:
1943+
case Mips::DDIV:
1944+
case Mips::DDIVU:
1945+
case Mips::DIVU_MMR6:
1946+
case Mips::DDIVU_MM64R6:
1947+
case Mips::DIV_MMR6:
1948+
case Mips::DDIV_MM64R6:
1949+
if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
1950+
Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
1951+
if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
1952+
Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
1953+
Warning(IDLoc, "dividing zero by zero");
1954+
else
1955+
Warning(IDLoc, "division by zero");
1956+
}
1957+
break;
1958+
}
1959+
18861960
// For PIC code convert unconditional jump to unconditional branch.
18871961
if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) &&
18881962
inPicMode()) {
@@ -3360,6 +3434,14 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
33603434
return false;
33613435
}
33623436

3437+
// Expand a integer division macro.
3438+
//
3439+
// Notably we don't have to emit a warning when encountering $rt as the $zero
3440+
// register, or 0 as an immediate. processInstruction() has already done that.
3441+
//
3442+
// The destination register can only be $zero when expanding (S)DivIMacro or
3443+
// D(S)DivMacro.
3444+
33633445
bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
33643446
const MCSubtargetInfo *STI, const bool IsMips64,
33653447
const bool Signed) {
@@ -3408,10 +3490,6 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
34083490
return true;
34093491

34103492
if (ImmValue == 0) {
3411-
if (RsReg == Mips::ZERO || RsReg == Mips::ZERO_64)
3412-
Warning(IDLoc, "dividing zero by zero");
3413-
else
3414-
Warning(IDLoc, "division by zero");
34153493
if (UseTraps)
34163494
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
34173495
else
@@ -3420,10 +3498,10 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
34203498
}
34213499

34223500
if (ImmValue == 1) {
3423-
TOut.emitRRR(Mips::ADDu, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
3501+
TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
34243502
return false;
34253503
} else if (Signed && ImmValue == -1) {
3426-
TOut.emitRRR(SubOp, RdReg, Mips::ZERO, RsReg, IDLoc, STI);
3504+
TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
34273505
return false;
34283506
} else {
34293507
if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
@@ -3436,51 +3514,31 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
34363514
return true;
34373515
}
34383516

3439-
if (RsReg == Mips::ZERO || RsReg == Mips::ZERO_64) {
3440-
if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)
3441-
Warning(IDLoc, "dividing zero by zero");
3442-
if (IsMips64) {
3443-
if (Signed && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
3444-
if (UseTraps) {
3445-
TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
3446-
return false;
3447-
}
3448-
3449-
TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
3450-
return false;
3451-
}
3452-
} else {
3453-
TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
3454-
return false;
3455-
}
3456-
}
3457-
3517+
// If the macro expansion of (d)div(u) would always trap or break, insert
3518+
// the trap/break and exit. This gives a different result to GAS. GAS has
3519+
// an inconsistency/missed optimization in that not all cases are handled
3520+
// equivalently. As the observed behaviour is the same, we're ok.
34583521
if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
3459-
Warning(IDLoc, "division by zero");
3460-
if (Signed) {
3461-
if (UseTraps) {
3462-
TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
3463-
return false;
3464-
}
3465-
3466-
TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
3522+
if (UseTraps) {
3523+
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
34673524
return false;
34683525
}
3526+
TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
3527+
return false;
34693528
}
34703529

3471-
// FIXME: The values for these two BranchTarget variables may be different in
3472-
// micromips. These magic numbers need to be removed.
3473-
unsigned BranchTargetNoTraps;
3474-
unsigned BranchTarget;
3530+
// Temporary label for first branch traget
3531+
MCContext &Context = TOut.getStreamer().getContext();
3532+
MCSymbol *BrTarget;
3533+
MCOperand LabelOp;
34753534

34763535
if (UseTraps) {
3477-
BranchTarget = IsMips64 ? 12 : 8;
34783536
TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
34793537
} else {
3480-
BranchTarget = IsMips64 ? 20 : 16;
3481-
BranchTargetNoTraps = 8;
34823538
// Branch to the li instruction.
3483-
TOut.emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, STI);
3539+
BrTarget = Context.createTempSymbol();
3540+
LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
3541+
TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
34843542
}
34853543

34863544
TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
@@ -3489,6 +3547,9 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
34893547
TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
34903548

34913549
if (!Signed) {
3550+
if (!UseTraps)
3551+
TOut.getStreamer().EmitLabel(BrTarget);
3552+
34923553
TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
34933554
return false;
34943555
}
@@ -3497,26 +3558,36 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
34973558
if (!ATReg)
34983559
return true;
34993560

3561+
if (!UseTraps)
3562+
TOut.getStreamer().EmitLabel(BrTarget);
3563+
35003564
TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
3565+
3566+
// Temporary label for the second branch target.
3567+
MCSymbol *BrTargetEnd = Context.createTempSymbol();
3568+
MCOperand LabelOpEnd =
3569+
MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));
3570+
3571+
// Branch to the mflo instruction.
3572+
TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
3573+
35013574
if (IsMips64) {
3502-
// Branch to the mflo instruction.
3503-
TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
35043575
TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
35053576
TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI);
35063577
} else {
3507-
// Branch to the mflo instruction.
3508-
TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
35093578
TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
35103579
}
35113580

35123581
if (UseTraps)
35133582
TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
35143583
else {
35153584
// Branch to the mflo instruction.
3516-
TOut.emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, STI);
3585+
TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
35173586
TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI);
35183587
TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
35193588
}
3589+
3590+
TOut.getStreamer().EmitLabel(BrTargetEnd);
35203591
TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
35213592
return false;
35223593
}

‎llvm/lib/Target/Mips/Mips32r6InstrInfo.td

+6
Original file line numberDiff line numberDiff line change
@@ -917,6 +917,12 @@ def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
917917
let AdditionalPredicates = [NotInMicroMips] in {
918918
def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
919919
}
920+
921+
def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
922+
GPR32Opnd:$rt)>, ISA_MIPS32R6;
923+
def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
924+
GPR32Opnd:$rt)>, ISA_MIPS32R6;
925+
920926
//===----------------------------------------------------------------------===//
921927
//
922928
// Patterns and Pseudo Instructions

‎llvm/lib/Target/Mips/Mips64InstrInfo.td

+45
Original file line numberDiff line numberDiff line change
@@ -835,3 +835,48 @@ def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
835835
"dmul\t$rs, $rt, $rd"> {
836836
let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips];
837837
}
838+
839+
let AdditionalPredicates = [NotInMicroMips] in {
840+
def DSDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
841+
(ins GPR64Opnd:$rs, GPR64Opnd:$rt),
842+
"ddiv\t$rd, $rs, $rt">,
843+
ISA_MIPS3_NOT_32R6_64R6;
844+
def DSDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
845+
(ins GPR64Opnd:$rs, imm64:$imm),
846+
"ddiv\t$rd, $rs, $imm">,
847+
ISA_MIPS3_NOT_32R6_64R6;
848+
def DUDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
849+
(ins GPR64Opnd:$rs, GPR64Opnd:$rt),
850+
"ddivu\t$rd, $rs, $rt">,
851+
ISA_MIPS3_NOT_32R6_64R6;
852+
def DUDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
853+
(ins GPR64Opnd:$rs, imm64:$imm),
854+
"ddivu\t$rd, $rs, $imm">,
855+
ISA_MIPS3_NOT_32R6_64R6;
856+
857+
// GAS expands 'div' and 'ddiv' differently when the destination
858+
// register is $zero and the instruction is in the two operand
859+
// form. 'ddiv' gets expanded, while 'div' is not expanded.
860+
861+
def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs,
862+
GPR64Opnd:$rs,
863+
GPR64Opnd:$rt), 0>,
864+
ISA_MIPS3_NOT_32R6_64R6;
865+
def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd,
866+
GPR64Opnd:$rd,
867+
imm64:$imm), 0>,
868+
ISA_MIPS3_NOT_32R6_64R6;
869+
870+
// GAS expands 'divu' and 'ddivu' differently when the destination
871+
// register is $zero and the instruction is in the two operand
872+
// form. 'ddivu' gets expanded, while 'divu' is not expanded.
873+
874+
def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt,
875+
GPR64Opnd:$rt,
876+
GPR64Opnd:$rs), 0>,
877+
ISA_MIPS3_NOT_32R6_64R6;
878+
def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd,
879+
GPR64Opnd:$rd,
880+
imm64:$imm), 0>,
881+
ISA_MIPS3_NOT_32R6_64R6;
882+
}

‎llvm/lib/Target/Mips/MipsInstrInfo.td

+17-33
Original file line numberDiff line numberDiff line change
@@ -2582,7 +2582,7 @@ def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
25822582
// Once the tablegen-erated errors are made better, this needs to be fixed and
25832583
// predicates needs to be restored.
25842584

2585-
def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2585+
def SDivMacro : MipsAsmPseudoInst<(outs GPR32NonZeroOpnd:$rd),
25862586
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
25872587
"div\t$rd, $rs, $rt">,
25882588
ISA_MIPS1_NOT_32R6_64R6;
@@ -2598,46 +2598,30 @@ def UDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
25982598
(ins GPR32Opnd:$rs, simm32:$imm),
25992599
"divu\t$rd, $rs, $imm">,
26002600
ISA_MIPS1_NOT_32R6_64R6;
2601-
def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
2602-
GPR32Opnd:$rs), 0>,
2603-
ISA_MIPS1_NOT_32R6_64R6;
2601+
2602+
2603+
def : MipsInstAlias<"div $rs, $rt", (SDIV GPR32ZeroOpnd:$rs,
2604+
GPR32Opnd:$rt), 0>,
2605+
ISA_MIPS1_NOT_32R6_64R6;
2606+
def : MipsInstAlias<"div $rs, $rt", (SDivMacro GPR32NonZeroOpnd:$rs,
2607+
GPR32NonZeroOpnd:$rs,
2608+
GPR32Opnd:$rt), 0>,
2609+
ISA_MIPS1_NOT_32R6_64R6;
26042610
def : MipsInstAlias<"div $rd, $imm", (SDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
26052611
simm32:$imm), 0>,
26062612
ISA_MIPS1_NOT_32R6_64R6;
2607-
def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
2613+
2614+
def : MipsInstAlias<"divu $rt, $rs", (UDIV GPR32ZeroOpnd:$rt,
2615+
GPR32Opnd:$rs), 0>,
2616+
ISA_MIPS1_NOT_32R6_64R6;
2617+
def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32NonZeroOpnd:$rt,
2618+
GPR32NonZeroOpnd:$rt,
26082619
GPR32Opnd:$rs), 0>,
26092620
ISA_MIPS1_NOT_32R6_64R6;
2621+
26102622
def : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
26112623
simm32:$imm), 0>,
26122624
ISA_MIPS1_NOT_32R6_64R6;
2613-
def DSDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2614-
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2615-
"ddiv\t$rd, $rs, $rt">,
2616-
ISA_MIPS64_NOT_64R6;
2617-
def DSDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2618-
(ins GPR32Opnd:$rs, imm64:$imm),
2619-
"ddiv\t$rd, $rs, $imm">,
2620-
ISA_MIPS64_NOT_64R6;
2621-
def DUDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2622-
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
2623-
"ddivu\t$rd, $rs, $rt">,
2624-
ISA_MIPS64_NOT_64R6;
2625-
def DUDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
2626-
(ins GPR32Opnd:$rs, imm64:$imm),
2627-
"ddivu\t$rd, $rs, $imm">,
2628-
ISA_MIPS64_NOT_64R6;
2629-
def : MipsInstAlias<"ddiv $rt, $rs", (DSDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
2630-
GPR32Opnd:$rs), 0>,
2631-
ISA_MIPS64_NOT_64R6;
2632-
def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
2633-
imm64:$imm), 0>,
2634-
ISA_MIPS64_NOT_64R6;
2635-
def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
2636-
GPR32Opnd:$rs), 0>,
2637-
ISA_MIPS64_NOT_64R6;
2638-
def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR32Opnd:$rd,
2639-
GPR32Opnd:$rd, imm64:$imm),
2640-
0>, ISA_MIPS64_NOT_64R6;
26412625

26422626
def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
26432627
"ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;

‎llvm/lib/Target/Mips/MipsRegisterInfo.td

+38-1
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,25 @@ class GPR32Class<list<ValueType> regTypes> :
290290
K0, K1, GP, SP, FP, RA)>;
291291

292292
def GPR32 : GPR32Class<[i32]>;
293+
294+
def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
295+
// Reserved
296+
ZERO)>;
297+
298+
def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add
299+
// Reserved
300+
AT,
301+
// Return Values and Arguments
302+
V0, V1, A0, A1, A2, A3,
303+
// Not preserved across procedure calls
304+
T0, T1, T2, T3, T4, T5, T6, T7,
305+
// Callee save
306+
S0, S1, S2, S3, S4, S5, S6, S7,
307+
// Not preserved across procedure calls
308+
T8, T9,
309+
// Reserved
310+
K0, K1, GP, SP, FP, RA)>;
311+
293312
def DSPR : GPR32Class<[v4i8, v2i16]>;
294313

295314
def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
@@ -317,7 +336,7 @@ def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
317336
S0, S2, S3, S4)>;
318337

319338
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
320-
// Reserved
339+
// Reserved
321340
ZERO_64, AT_64,
322341
// Return Values and Arguments
323342
V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
@@ -479,6 +498,16 @@ def GPR64AsmOperand : MipsAsmRegOperand {
479498
let PredicateMethod = "isGPRAsmReg";
480499
}
481500

501+
def GPR32ZeroAsmOperand : MipsAsmRegOperand {
502+
let Name = "GPR32ZeroAsmReg";
503+
let PredicateMethod = "isGPRZeroAsmReg";
504+
}
505+
506+
def GPR32NonZeroAsmOperand : MipsAsmRegOperand {
507+
let Name = "GPR32NonZeroAsmReg";
508+
let PredicateMethod = "isGPRNonZeroAsmReg";
509+
}
510+
482511
def GPR32AsmOperand : MipsAsmRegOperand {
483512
let Name = "GPR32AsmReg";
484513
let PredicateMethod = "isGPRAsmReg";
@@ -550,6 +579,14 @@ def MSACtrlAsmOperand : MipsAsmRegOperand {
550579
let Name = "MSACtrlAsmReg";
551580
}
552581

582+
def GPR32ZeroOpnd : RegisterOperand<GPR32ZERO> {
583+
let ParserMatchClass = GPR32ZeroAsmOperand;
584+
}
585+
586+
def GPR32NonZeroOpnd : RegisterOperand<GPR32NONZERO> {
587+
let ParserMatchClass = GPR32NonZeroAsmOperand;
588+
}
589+
553590
def GPR32Opnd : RegisterOperand<GPR32> {
554591
let ParserMatchClass = GPR32AsmOperand;
555592
}

‎llvm/test/MC/Mips/macro-ddiv.s

+55-40
Original file line numberDiff line numberDiff line change
@@ -1,73 +1,82 @@
1-
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 | \
1+
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | \
22
# RUN: FileCheck %s --check-prefix=CHECK-NOTRAP
3-
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
3+
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 \
44
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
55

66
ddiv $25,$11
7-
# CHECK-NOTRAP: bne $11, $zero, 8 # encoding: [0x15,0x60,0x00,0x02]
7+
# CHECK-NOTRAP: bne $11, $zero, .Ltmp0 # encoding: [0x15,0x60,A,A]
8+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
89
# CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
910
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
11+
# CHECK-NOTRAP: .Ltmp0
1012
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
11-
# CHECK-NOTRAP: bne $11, $1, 20 # encoding: [0x15,0x61,0x00,0x05]
13+
# CHECK-NOTRAP: bne $11, $1, .Ltmp1 # encoding: [0x15,0x61,A,A]
14+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
1215
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
1316
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
14-
# CHECK-NOTRAP: bne $25, $1, 8 # encoding: [0x17,0x21,0x00,0x02]
17+
# CHECK-NOTRAP: bne $25, $1, .Ltmp1 # encoding: [0x17,0x21,A,A]
18+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
1519
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
1620
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
21+
# CHECK-NOTRAP: .Ltmp1
1722
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
23+
1824
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
1925
# CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
2026
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
21-
# CHECK-TRAP: bne $11, $1, 12 # encoding: [0x15,0x61,0x00,0x03]
27+
# CHECK-TRAP: bne $11, $1, .Ltmp0 # encoding: [0x15,0x61,A,A]
28+
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
2229
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
2330
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
2431
# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
32+
# CHECK-TRAP: .Ltmp0:
2533
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
2634

2735
ddiv $24,$12
28-
# CHECK-NOTRAP: bne $12, $zero, 8 # encoding: [0x15,0x80,0x00,0x02]
36+
# CHECK-NOTRAP: bne $12, $zero, .Ltmp2 # encoding: [0x15,0x80,A,A]
37+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
2938
# CHECK-NOTRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
3039
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
40+
# CHECK-NOTRAP: .Ltmp2:
3141
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
32-
# CHECK-NOTRAP: bne $12, $1, 20 # encoding: [0x15,0x81,0x00,0x05]
42+
# CHECK-NOTRAP: bne $12, $1, .Ltmp3 # encoding: [0x15,0x81,A,A]
43+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
3344
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
3445
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
35-
# CHECK-NOTRAP: bne $24, $1, 8 # encoding: [0x17,0x01,0x00,0x02]
46+
# CHECK-NOTRAP: bne $24, $1, .Ltmp3 # encoding: [0x17,0x01,A,A]
47+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
3648
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
3749
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
50+
# CHECK-NOTRAP: .Ltmp3
3851
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
52+
3953
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
4054
# CHECK-TRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
4155
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
42-
# CHECK-TRAP: bne $12, $1, 12 # encoding: [0x15,0x81,0x00,0x03]
56+
# CHECK-TRAP: bne $12, $1, .Ltmp1 # encoding: [0x15,0x81,A,A]
57+
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
4358
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
4459
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
4560
# CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
61+
# CHECK-TRAP: .Ltmp1:
4662
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
4763

4864
ddiv $25,$0
4965
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
5066
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
5167

5268
ddiv $0,$9
53-
# CHECK-NOTRAP: bne $9, $zero, 8 # encoding: [0x15,0x20,0x00,0x02]
5469
# CHECK-NOTRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
55-
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
56-
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
57-
# CHECK-NOTRAP: bne $9, $1, 20 # encoding: [0x15,0x21,0x00,0x05]
58-
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
59-
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
60-
# CHECK-NOTRAP: bne $zero, $1, 8 # encoding: [0x14,0x01,0x00,0x02]
61-
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
62-
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
63-
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
70+
6471
# CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
6572
# CHECK-TRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
6673
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
67-
# CHECK-TRAP: bne $9, $1, 12 # encoding: [0x15,0x21,0x00,0x03]
74+
# CHECK-TRAP: bne $9, $1, .Ltmp2 # encoding: [0x15,0x21,A,A]
75+
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
6876
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
6977
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
7078
# CHECK-TRAP: teq $zero, $1, 6 # encoding: [0x00,0x01,0x01,0xb4]
79+
# CHECH-TRAP: .Ltmp2:
7180
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
7281

7382
ddiv $0,$0
@@ -83,8 +92,8 @@
8392
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
8493

8594
ddiv $4,1
86-
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
87-
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
95+
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
96+
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
8897

8998
ddiv $4,-1
9099
# CHECK-NOTRAP: dsub $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2e]
@@ -190,24 +199,32 @@
190199
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
191200

192201
ddiv $4,$5,$6
193-
# CHECK-NOTRAP: bne $6, $zero, 8 # encoding: [0x14,0xc0,0x00,0x02]
202+
# CHECK-NOTRAP: bne $6, $zero, .Ltmp6 # encoding: [0x14,0xc0,A,A]
203+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp6-4, kind: fixup_Mips_PC16
194204
# CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
195-
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
205+
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
206+
# CHECK-NOTRAP: .Ltmp6:
196207
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
197-
# CHECK-NOTRAP: bne $6, $1, 20 # encoding: [0x14,0xc1,0x00,0x05]
208+
# CHECK-NOTRAP: bne $6, $1, .Ltmp7 # encoding: [0x14,0xc1,A,A]
209+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp7-4, kind: fixup_Mips_PC16
198210
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
199211
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
200-
# CHECK-NOTRAP: bne $5, $1, 8 # encoding: [0x14,0xa1,0x00,0x02]
212+
# CHECK-NOTRAP: bne $5, $1, .Ltmp7 # encoding: [0x14,0xa1,A,A]
213+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp7-4, kind: fixup_Mips_PC16
201214
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
202-
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
215+
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
216+
# CHECK-NOTRAP: .Ltmp7:
203217
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
218+
204219
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
205220
# CHECK-TRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
206221
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
207-
# CHECK-TRAP: bne $6, $1, 12 # encoding: [0x14,0xc1,0x00,0x03]
222+
# CHECK-TRAP: bne $6, $1, .Ltmp3 # encoding: [0x14,0xc1,A,A]
223+
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
208224
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
209225
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
210226
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
227+
# CHECK-TRAP: .Ltmp3:
211228
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
212229

213230
ddiv $4,$5,$0
@@ -231,8 +248,8 @@
231248
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
232249

233250
ddiv $4,$5,1
234-
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
235-
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
251+
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
252+
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
236253

237254
ddiv $4,$5,-1
238255
# CHECK-NOTRAP: dsub $4, $zero, $5 # encoding: [0x00,0x05,0x20,0x2e]
@@ -328,12 +345,10 @@
328345
# CHECK-NOTRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
329346
# CHECK-NOTRAP: ddiv $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1e]
330347
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
331-
# CHECK-TRAP: addiu $1, $zero, 15 # encoding: [0x24,0x01,0x00,0x0f]
332-
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
333-
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
334-
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
335-
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
336-
# CHECK-TRAP: ddiv $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1e]
337-
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
338-
339-
348+
# CHECK-TRAP: addiu $1, $zero, 15 # encoding: [0x24,0x01,0x00,0x0f]
349+
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
350+
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
351+
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
352+
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
353+
# CHECK-TRAP: ddiv $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1e]
354+
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]

‎llvm/test/MC/Mips/macro-ddivu.s

+18-30
Original file line numberDiff line numberDiff line change
@@ -1,52 +1,48 @@
1-
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 | \
1+
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | \
22
# RUN: FileCheck %s --check-prefix=CHECK-NOTRAP
3-
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
3+
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 \
44
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
55

66
ddivu $25,$11
7-
# CHECK-NOTRAP: bne $11, $zero, 8 # encoding: [0x15,0x60,0x00,0x02]
7+
# CHECK-NOTRAP: bne $11, $zero, .Ltmp0 # encoding: [0x15,0x60,A,A]
8+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
89
# CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
910
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
11+
# CHECK-NOTRAP: .Ltmp0
1012
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
1113
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
1214
# CHECK-TRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
1315
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
1416

1517
ddivu $24,$12
16-
# CHECK-NOTRAP: bne $12, $zero, 8 # encoding: [0x15,0x80,0x00,0x02]
18+
# CHECK-NOTRAP: bne $12, $zero, .Ltmp1 # encoding: [0x15,0x80,A,A]
19+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
1720
# CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
1821
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
22+
# CHECK-NOTRAP: .Ltmp1
1923
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
2024
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
2125
# CHECK-TRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
2226
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
2327

2428
ddivu $25,$0
25-
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
26-
# CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
2729
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
28-
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
2930
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
30-
# CHECK-TRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
31-
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
3231

3332
ddivu $0,$9
34-
# CHECK-NOTRAP: bne $9, $zero, 8 # encoding: [0x15,0x20,0x00,0x02]
33+
# CHECK-NOTRAP: bne $9, $zero, .Ltmp2 # encoding: [0x15,0x20,A,A]
34+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
3535
# CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
3636
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
37+
# CHECK-NOTRAP: .Ltmp2
3738
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
3839
# CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
3940
# CHECK-TRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
4041
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
4142

4243
ddivu $0,$0
43-
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
44-
# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
4544
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
46-
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
4745
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
48-
# CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
49-
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
5046

5147
ddivu $4,0
5248
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
@@ -57,8 +53,8 @@
5753
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
5854

5955
ddivu $4,1
60-
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
61-
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
56+
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
57+
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
6258

6359
ddivu $4,-1
6460
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
@@ -159,31 +155,23 @@
159155
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
160156

161157
ddivu $4,$5,$6
162-
# CHECK-NOTRAP: bne $6, $zero, 8 # encoding: [0x14,0xc0,0x00,0x02]
158+
# CHECK-NOTRAP: bne $6, $zero, .Ltmp3 # encoding: [0x14,0xc0,A,A]
159+
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
163160
# CHECK-NOTRAP: ddivu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1f]
164161
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
162+
# CHECK-NOTRAP: .Ltmp3:
165163
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
166164
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
167165
# CHECK-TRAP: ddivu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1f]
168166
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
169167

170168
ddivu $4,$5,$0
171-
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
172-
# CHECK-NOTRAP: ddivu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1f]
173169
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
174-
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
175170
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
176-
# CHECK-TRAP: ddivu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1f]
177-
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
178171

179172
ddivu $4,$0,$0
180-
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
181-
# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
182173
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
183-
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
184174
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
185-
# CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
186-
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
187175

188176
ddivu $0, $4, $5
189177
# CHECK-NOTRAP: ddivu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1f]
@@ -202,8 +190,8 @@
202190
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
203191

204192
ddivu $4,$5,1
205-
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
206-
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
193+
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
194+
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
207195

208196
ddivu $4,$5,-1
209197
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]

‎llvm/test/MC/Mips/macro-div-bad.s

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
# RUN: FileCheck %s --check-prefix=NOT-R6
99

1010
.text
11-
div $25, $11
11+
div $25, 11
1212
# R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
1313

1414
div $25, $0

‎llvm/test/MC/Mips/macro-div.s

+45-24
Original file line numberDiff line numberDiff line change
@@ -4,41 +4,55 @@
44
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
55

66
div $25,$11
7-
# CHECK-NOTRAP: bnez $11, 8 # encoding: [0x15,0x60,0x00,0x02]
7+
# CHECK-NOTRAP: bnez $11, $tmp0 # encoding: [0x15,0x60,A,A]
8+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp0)-4, kind: fixup_Mips_PC16
89
# CHECK-NOTRAP: div $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1a]
9-
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
10+
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
11+
# CHECK-NOTRAP: $tmp0:
1012
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
11-
# CHECK-NOTRAP: bne $11, $1, 16 # encoding: [0x15,0x61,0x00,0x04]
13+
# CHECK-NOTRAP: bne $11, $1, $tmp1 # encoding: [0x15,0x61,A,A]
14+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
1215
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
13-
# CHECK-NOTRAP: bne $25, $1, 8 # encoding: [0x17,0x21,0x00,0x02]
16+
# CHECK-NOTRAP: bne $25, $1, $tmp1 # encoding: [0x17,0x21,A,A]
17+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
1418
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
1519
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
20+
# CHECK-NOTRAP: $tmp1:
1621
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
1722
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
1823
# CHECK-TRAP: div $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1a]
1924
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
20-
# CHECK-TRAP: bne $11, $1, 8 # encoding: [0x15,0x61,0x00,0x02]
25+
# CHECK-TRAP: bne $11, $1, $tmp0 # encoding: [0x15,0x61,A,A]
26+
# CHECK-TRAP: # fixup A - offset: 0, value: ($tmp0)-4, kind: fixup_Mips_PC16
2127
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
2228
# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
29+
# CHECK-TRAP: $tmp0:
2330
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
2431

2532
div $24,$12
26-
# CHECK-NOTRAP: bnez $12, 8 # encoding: [0x15,0x80,0x00,0x02]
33+
# CHECK-NOTRAP: bnez $12, $tmp2 # encoding: [0x15,0x80,A,A]
34+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp2)-4, kind: fixup_Mips_PC16
2735
# CHECK-NOTRAP: div $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1a]
28-
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
36+
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
37+
# CHECK-NOTRAP: $tmp2:
2938
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
30-
# CHECK-NOTRAP: bne $12, $1, 16 # encoding: [0x15,0x81,0x00,0x04]
39+
# CHECK-NOTRAP: bne $12, $1, $tmp3 # encoding: [0x15,0x81,A,A]
40+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp3)-4, kind: fixup_Mips_PC16
3141
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
32-
# CHECK-NOTRAP: bne $24, $1, 8 # encoding: [0x17,0x01,0x00,0x02]
42+
# CHECK-NOTRAP: bne $24, $1, $tmp3 # encoding: [0x17,0x01,A,A]
43+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp3)-4, kind: fixup_Mips_PC16
3344
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
34-
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
45+
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
46+
# CHECK-NOTRAP: $tmp3:
3547
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
3648
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
3749
# CHECK-TRAP: div $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1a]
3850
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
39-
# CHECK-TRAP: bne $12, $1, 8 # encoding: [0x15,0x81,0x00,0x02]
51+
# CHECK-TRAP: bne $12, $1, $tmp1 # encoding: [0x15,0x81,A,A]
52+
# CHECK-TRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
4053
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
4154
# CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
55+
# CHECK-TRAP: $tmp1:
4256
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
4357

4458
div $25,$0
@@ -62,8 +76,8 @@
6276
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
6377

6478
div $4,1
65-
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
66-
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
79+
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
80+
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
6781

6882
div $4,-1
6983
# CHECK-NOTRAP: neg $4, $4 # encoding: [0x00,0x04,0x20,0x22]
@@ -112,31 +126,38 @@
112126
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
113127

114128
div $4,$5,$6
115-
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
129+
# CHECK-NOTRAP: bnez $6, $tmp4 # encoding: [0x14,0xc0,A,A]
130+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp4)-4, kind: fixup_Mips_PC16
116131
# CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1a]
117-
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
132+
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
133+
# CHECK-NOTRAP: $tmp4:
118134
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
119-
# CHECK-NOTRAP: bne $6, $1, 16 # encoding: [0x14,0xc1,0x00,0x04]
135+
# CHECK-NOTRAP: bne $6, $1, $tmp5 # encoding: [0x14,0xc1,A,A]
136+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp5)-4, kind: fixup_Mips_PC16
120137
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
121-
# CHECK-NOTRAP: bne $5, $1, 8 # encoding: [0x14,0xa1,0x00,0x02]
138+
# CHECK-NOTRAP: bne $5, $1, $tmp5 # encoding: [0x14,0xa1,A,A]
139+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp5)-4, kind: fixup_Mips_PC16
122140
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
123141
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
142+
# CHECK-NOTRAP: $tmp5:
124143
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
125144
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
126145
# CHECK-TRAP: div $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1a]
127146
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
128-
# CHECK-TRAP: bne $6, $1, 8 # encoding: [0x14,0xc1,0x00,0x02]
147+
# CHECK-TRAP: bne $6, $1, $tmp2 # encoding: [0x14,0xc1,A,A]
148+
# CHECK-TRAP: # fixup A - offset: 0, value: ($tmp2)-4, kind: fixup_Mips_PC16
129149
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
130150
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
131-
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
151+
# CHECK-TRAP: $tmp2:
152+
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
132153

133154
div $4,$5,$0
134155
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
135156
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
136157

137158
div $4,$0,$0
138-
# CHECK-NOTRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a]
139-
# CHECK-TRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a]
159+
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
160+
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
140161

141162
div $0,$4,$5
142163
# CHECK-NOTRAP: div $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1a]
@@ -151,8 +172,8 @@
151172
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
152173

153174
div $4,$5,1
154-
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
155-
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
175+
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
176+
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
156177

157178
div $4,$5,-1
158179
# CHECK-NOTRAP: neg $4, $5 # encoding: [0x00,0x05,0x20,0x22]
@@ -198,4 +219,4 @@
198219
# CHECK-TRAP: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
199220
# CHECK-TRAP: ori $1, $1, 42405 # encoding: [0x34,0x21,0xa5,0xa5]
200221
# CHECK-TRAP: div $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1a]
201-
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
222+
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]

‎llvm/test/MC/Mips/macro-divu-bad.s

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
# RUN: FileCheck %s --check-prefix=NOT-R6
99

1010
.text
11-
divu $25, $11
11+
divu $25, 11
1212
# R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
1313

1414
divu $25, $0

‎llvm/test/MC/Mips/macro-divu.s

+10-17
Original file line numberDiff line numberDiff line change
@@ -4,22 +4,23 @@
44
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
55

66
divu $25,$11
7-
# CHECK-NOTRAP: bnez $11, 8 # encoding: [0x15,0x60,0x00,0x02]
7+
# CHECK-NOTRAP: bnez $11, $tmp0 # encoding: [0x15,0x60,A,A]
8+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp0)-4, kind: fixup_Mips_PC16
89
# CHECK-NOTRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
910
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
11+
# CHECK-NOTRAP: $tmp0:
1012
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
1113

1214
divu $24,$12
13-
# CHECK-NOTRAP: bnez $12, 8 # encoding: [0x15,0x80,0x00,0x02]
15+
# CHECK-NOTRAP: bnez $12, $tmp1 # encoding: [0x15,0x80,A,A]
16+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
1417
# CHECK-NOTRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
1518
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
19+
# CHECK-NOTRAP: $tmp1:
1620
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
1721

1822
divu $25,$0
19-
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
20-
# CHECK-NOTRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
2123
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
22-
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
2324

2425
divu $0,$9
2526
# CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
@@ -28,22 +29,18 @@
2829
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
2930

3031
divu $4,$5,$6
31-
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
32+
# CHECK-NOTRAP: bnez $6, $tmp2 # encoding: [0x14,0xc0,A,A]
33+
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp2)-4, kind: fixup_Mips_PC16
3234
# CHECK-NOTRAP: divu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1b]
3335
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
36+
# CHECK-NOTRAP: $tmp2:
3437
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
3538

3639
divu $4,$5,$0
37-
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
38-
# CHECK-NOTRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
3940
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
40-
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
4141

4242
divu $4,$0,$0
43-
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
44-
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
4543
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
46-
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
4744

4845
divu $0, $4, $5
4946
# CHECK-NOTRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
@@ -60,8 +57,6 @@
6057

6158
divu $25,$0
6259
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
63-
# CHECK-TRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
64-
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
6560

6661
divu $0,$9
6762
# CHECK-TRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
@@ -76,13 +71,11 @@
7671

7772
divu $4,$5,$0
7873
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
79-
# CHECK-TRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
80-
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
8174

8275
divu $4,$0,$0
8376
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
8477
# CHECK-TRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
8578
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
8679

8780
divu $0, $4, $5
88-
# CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
81+
# CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]

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